Subject: RE: [sv-bc] logic -vs- ulogic
From: Jay Lawrence (lawrence@cadence.com)
Date: Mon Apr 14 2003 - 09:54:10 PDT
I love the suggestion Cliff and have each time you've made it!
However, I have to agree with David's comment from a few days ago that
this is not a last minute editing sort of cleanup and it is too late for
this change.
I'll see you in the IEEE VSG meeting to discuss it ...
Jay
> -----Original Message-----
> From: Clifford E. Cummings [mailto:cliffc@sunburst-design.com]
> Sent: Monday, April 14, 2003 12:51 PM
> To: sv-ec@eda.org; sv-bc@eda.org
> Subject: [sv-bc] logic -vs- ulogic
>
>
> Hi, All -
>
> I have raised issue this a number of times. I don't know if
> it was ever
> formally voted.
>
> I still think if we are going to have these "logic" and "bit"
> types, that
> we would be doing the Verilog and VHDL communities a favor by
> at least
> choosing the keywords: ulogic, ubit.
>
> In VHDL, std_logic_type is the resolved type. std_ulogic_type is the
> unresolved type. I don't see a compelling reason to confuse
> the poor VHDL
> engineers by swapping the definitions on them.
>
> Not only that, but I am guessing the "ulogic" will kill fewer
> existing
> designs that "logic" (same argument for "ubit" vs. "bit").
>
> This is a relatively easy global change, one that might be less
> controversial when it is addressed by the IEEE VSG.
>
> Thoughts? Is this possible?
>
> Regards - Cliff
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com
> Expert Verilog, Synthesis and Verification Training
>
>
>
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