Subject: [sv-bc] Re: [sv-ec] Assignments in event expressions
From: Dave Rich (David.Rich@synopsys.com)
Date: Mon Apr 14 2003 - 21:20:42 PDT
Hi Jay,
Yes, I found this too. SV-BC-85 made this section obsolete.
David posted this as LRM-109
Dave
Jay Lawrence wrote:
>David Smith, Dave Rich, and Johny Srouji,
>
>While working on other issues surrounding SystemVerilog this evening I
>came across an obvious conflict in the Draft 4 LRM. In section 7.3 it
>says: "It shall be illegal to include an assignment expression in an
>event control". Section 8.11 is entitled "Assignment expressions within
>event controls" and explains how they will be handled.
>
>Can we possibly just delete section 8.11 and leave these as illegal? It
>appears to me from the change bars and editing that the sv-ec added
>section 7.3 to eliminate a nasty situation and that 8.11 existed in the
>3.0 standard.
>
>Jay
>
>
>
>===================================
>Jay Lawrence
>Senior Architect
>Functional Verification
>Cadence Design Systems, Inc.
>(978) 262-6294
>lawrence@cadence.com
>===================================
>
>
>
>
-- -- Dave Rich Principal Engineer, CAE, VTG Tel: 650-584-4026 Cell: 510-589-2625 DaveR@Synopsys.com
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