Subject: RE: [sv-bc] Assignments in expressions as an atomic operator
From: David W. Smith (david.smith@synopsys.com)
Date: Thu Apr 17 2003 - 10:26:40 PDT
Greetings,
The change that Stu is referring to is:
Section 9.1
LRM-254
Changes:
SystemVerilog creates a thread of execution for each initial or always
block, for each parallel statement in a fork...join block and for each
dynamic process. Each continuous assignment can also be considered its own
thread. Execution of each thread can be interrupted between statements at a
semicolon, but a single statement (not a block) containing no user task or
function call cannot be uninterrupted. This allows atomic test-and-set using
assignment operators in an if statement.
Section 9.7
LRM-254
Changes:
Execution of each thread can be interrupted between statements at a
semicolon, but a single statement (not a block) containing neither a user
task call nor a function call shall not be interrupted. This allows atomic
test-and-set using assignment operators in an if statement.
Regards
David
-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Stuart
Sutherland
Sent: Thursday, April 17, 2003 10:07 AM
To: David W. Smith; 'Jay Lawrence'; sv-bc@eda.org
Subject: RE: [sv-bc] Assignments in expressions as an atomic operator
LRM-254 completely removed the sentences regarding both interrupting the
thread and test-and-set IN SECTION 9.7 ONLY. In Section 9.1, only the
reference to test-and-set was deleted. The part about interrupting the
thread was not removed. Was this the intent of the change?
Stu
At 09:15 AM 4/17/2003, David W. Smith wrote:
>Greetings,
>
>After discussion with Arturo and Dave Rich about this there was
>agreement that this had been decided to be removed. LRM-254 has been
>created and should be fixed in Draft 5.
>
>Regards
>David
>
>-----Original Message-----
>From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Jay
>Lawrence
>Sent: Wednesday, April 16, 2003 5:19 PM
>To: sv-bc@eda.org
>Cc: David Smith
>Subject: [sv-bc] Assignments in expressions as an atomic operator
>
>
>
>
>
>I know it is very late for this comment but in working on SystemVerilog
>related tasks I came across the following in Sections 9.1 and 9.7.
>
> "Execution of each thread can be interrupted between
>statements at a semicolon, but a single statement (not a block)
>containing no user task or function call shall not be interrupted. This
>allows atomic test-and-set using assignment operators in an if
>statement"
>
>This was discussed at length in one of the face-to-face sv-bc meetings.
>I believe it was the one in January. I thought it was agreed that this
>was a change to the simulation semantics that was to be removed from
>the LRM. I apologize for not catching this early in the meeting minutes
>or subsequent review. These little paragraphs can be tricky.
>
>I would ask that an LRM issue be created for this item.
>
>Thanks,
>
>Jay
>
>
>===================================
>Jay Lawrence
>Senior Architect
>Functional Verification
>Cadence Design Systems, Inc.
>(978) 262-6294
>lawrence@cadence.com
>===================================
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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