[sv-bc] SystemVerilog 3.1 draft 5 available for review

Subject: [sv-bc] SystemVerilog 3.1 draft 5 available for review
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Fri Apr 18 2003 - 12:02:37 PDT

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All,

Draft 5 of the SystemVerilog 3.1 LRM is now available to download and
review. The PDF file can be found at:

http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft5.pdf

This draft has all the mark ups from previous drafts removed, and only
shows the changes between draft 4 and draft 5. It also has a complete BNF,
with the BNF excerpts added to every chapter. As you review your favorite
portions (or assigned portions), please make sure that I snipped the
correct portions of the BNF in each excerpt. The last major piece to
complete is adding the markers on every page to create a useful index...

Stu

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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