Subject: [sv-bc] FW: Unpacked arrays
From: David W. Smith (david.smith@synopsys.com)
Date: Tue Apr 22 2003 - 15:24:25 PDT
Changes in LRM-321 per Dave Rich.
Regards
David
-----Original Message-----
From: Dave Rich [mailto:David.Rich@Synopsys.COM]
Sent: Monday, April 21, 2003 4:30 PM
To: David W. Smith; Arturo Salz
Subject: Unpacked arrays
I don't know how this got messed up
In section 4.2 page 26/27, delete the striked text
Packed arrays can only be made of the single bit types: (bit, logic, reg,
wire, and the other net types) and
recursively other packed arrays and packed structures. Unpacked arrays can
be made up of any type.
Integer types with predefined widths cannot have packed array dimensions
declared. These types are: byte,
shortint, int, longint, and integer. An integer type with a predefined width
can be treated as a single
dimension packed array. The packed dimensions of these integer types shall
be numbered down to 0, such that
the right-most index is 0.
byte c2; // same as bit [7:0] c2;
integer i1; // same as logic signed [31:0] i1;
Unpacked arrays can be made of any scalar (non-unpacked-array) singular
type. SystemVerilog enhances
fixed-size unpacked arrays in that in addition to all other SystemVerilog
variable types, unpacked arrays may also be
made of object handles (see Section 11.4) and events (see Section 13.5).
----
Dave Rich
Principal Engineer, CAE, VTG
Tel: 650-584-4026
Cell: 510-589-2625
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