Subject: [sv-bc] SystemVerilog Workshop At DAC on June 2 -- Room 304, Anaheim Conv ention Center
From: Vassilios.Gerousis@Infineon.Com
Date: Sun May 04 2003 - 01:27:11 PDT
Please invite engineers and managers from your companies to attend
SystemVerilog
Workshop at DAC 2003. It is free all DAC attendees (Exhibitors, Exhibit
attendees, DAC regular sessions attendees, etc.). Free Lunch is Provided.
http://www.accellera.org/SystemVerilogWorkshop.html
<http://www.accellera.org/SystemVerilogWorkshop.html>
You should register to save a place with Accellera Organization (use web
address below). To enter the Workshop room you must also be registered at
DAC (Exhibit registration is also free at DAC). Seating is limited
http://www.accellera.org/sysver.html <http://www.accellera.org/sysver.html>
====================================================
SystemVerilog: The Next Generation Verilog Language
June 2, 2003
9:00am - 4:30 PM
Room 304, Anaheim Convention Center
SystemVerilog, an Accellera Approved Standard, offers designers and
verification engineers a
new Hardware Design and Verification Language (HDVL). SystemVerilog is an
evolution of
IEEE 1364 Verilog standards that extends Verilog into the high-level design
and verification
domains. It provides high-level design constructs for concise design and
adds two verification
components: Verilog-Based Testbench constructs and Verilog-Based Assertions.
These new
additions enable the industry to develop revolutionary tools to support a
Design for Verification
methodology. It encourages designers/verification engineers to use
productive concise design,
high-level test bench automation, and assertion-based verification.
Both designers and verification engineers will learn the details of
Accellera's System Verilog
HDVL language and new methodologies of Design for Verification. The tutorial
will provide
details of the SystemVerilog language, syntax and semantics presented by
experts. Also,
leading-edge designers and verification users from Intel, Infineon, and
Verification Central will
share their real life experiences.
1. SystemVerilog Motivation and Methodologies: Vassilios Gerousis,
Infineon
2. SystemVerilog Language Components
a. SystemVerilog for Design
* SystemVerilog Introduction: Johny Srouji, Intel
* User Experience With SystemVerilog for Design: Matt
Maidment, Intel
This session provides details on synthesizable SystemVerilog for
design. It
describes higher-level language features including data
structures, user-defined
datatypes, and powerful encapsulated interfaces for RTL design.
The high-level
language features provide higher productivity by describing
designs more
concisely using less code and with higher quality. The User
Experience session
will share examples of these new SystemVerilog design constructs
for effective
RTL design.
b. SystemVerilog for Describing Testbenches
* SystemVerilog Testbench & Verification Tutorial: Tom
Fitzpatrick,
Synopsys
* User Experience: Writing Testbenches Using SystemVerilog:
Faisal
Haque, Verification Central
This session will describe the new testbench features of the
language and show
productive verification methods for testbench automation in
SystemVerilog. We
will show how these features can be applied to create directed,
random,
pseudo-random tests, and other methods to automate testbenches.
The user
experience will provide methodology guidance in using the
SystemVerilog
testbench automation features. The methodology will be described
first then,
examples extracted from real designs will be shown to
demonstrate the different
TestBench features of SystemVerilog.
c. SystemVerilog Assertions (SVA)
* SVA Tutorial: Bassam Tabbara, Novas
* SVA Technology and User Experience: Alon Flaisher, Intel
* User Experience "Using Assertions With Your Testbench":
Jon Michelson,Verification Central
The first segment will introduce assertion constructs and their
usage in
SystemVerilog to provide design and verification engineers with
a powerful
language to do assertion-based verification. Assertion-based
verification provides
a way to capture specifications as assertions in the design and
reuse the same
assertions for simulation, formal verification, hardware
acceleration and other
technologies, providing large gains in verification
productivity. SystemVerilog
assertions contain a powerful set of assertion, sequence and
property
specification features that are user-friendly with Verilog
syntax and mathematical
semantics. The user experience will cover the assertion-based
verification
methodology and experiences with it, including the additional
power that can be
gained by writing an "assertion-aware" testbench.
d. SystemVerilog C Interface and APIs
* C / API technology and User Experience: Doug Warmke,
Mentor Graphics
The API provides a standard way for other tools to work with
SystemVerilog
with regard to assertions and coverage. The C interface provides
a way for C
and SystemVerilog to execute models together. Any model in
SystemVerilog can
call C functions and C code can call SystemVerilog functions.
This is a powerful
capability that provides a direct C interface to SystemVerilog
and opens the
doors for better hardware and software modeling, and
verification.
3. How to Combine SystemVerilog and IEEE 2001 Verilog: Stuart
Sutherland
4. Companies and Tools Supporting SystemVerilog: Vassilios Gerousis
5. Discussion, Questions and Conclusions
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