Subject: [sv-bc] SV Chairs and Champions Response to Negative Ballot Comments of C adence
From: Vassilios.Gerousis@Infineon.Com
Date: Fri May 16 2003 - 03:07:30 PDT
Dear SystemVerilog Committee Members,
The SV Chairs and Champions have put together a response document
that address every comment provided by Cadence that was submitted as part of
their negative vote in the technical Committee.
It is important to emphasize that Cadence technical members had
provided positive influence in the contents of the LRM. As examples,
Cadence with other members helped in the development of foundational
elements like SystemVerilog 3.1 simulation semantics and also in the Unified
Assertion Kernel development (developed for SV 3.1 and PSL 1.1) and final
completion.
In regards to the technical response, I would like to emphasize the
following points:
1- Some of the Cadence comments should have been provided during either the
LRM development period or the LRM review periods. The technical committee
went through the review process starting with draft 3 through draft 6,
Cadence elected not to provide these specific comments during this review
period.
2- Several of the Cadence comments were discussed, debated, with proposals
in technical committee meetings. Once the committee vote to accept or reject
the proposals, it is understood that the item is closed. One company, if
they do not like the results, cannot dictate what the resolution should be
or change the results of the majority.
a- Cadence's votes on the vast majority of the issues were in line
with the agreed-upon decisions. The number of times they voted against a
given decision was much less.
3- Most issues which were raised by a committee member, were backed up by a
written proposal which was submitted to the reflector before the meetings.
Committee members had the chance to read, comment, object or raise a counter
part proposal through email and during the meeting.
a- Cadence raised few issues that the committee eventually put them
on the shelf. None of those issues were backed up by a written proposal.
4- It is instructive to note that many of the issues raised are related to
the already approved Accellera SystemVerilog 3.0 version of the LRM (that
Cadence also participated in and provided positive vote in the technical
committee). The ratio is 42% from 3.0 and 58% from 3.1.
SystemVerilog 3.1 is a monumental effort that breaks new grounds for
the verification industry. With greater than 2/3 majority, you have
developed and approved the technical content of SystemVerilog 3.1. It is
time for Accellera Community and the whole industry to celebrate the
technical approval of SystemVerilog 3.1.
<<SVChairsChampionsResponse.pdf>>
Best Regards
Vassilios
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Dr. Vassilios Gerousis
Chief Scientist - Senior Principal Design Methodology
Infineon Technologies
CL DAT CS, MchB
D-81541 Munich
Germany
Balanstr. 73
Office Telephone: +49-89-234-21342
Fax: +49-89-234-23650
Email: Vassilios.Gerousis@infineon.com
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