Subject: Re: [sv-bc] SystemVerilog 3.1 Is An Accellera Standard
From: Mohamed Salem (mohamed.salem@handasarabia.org)
Date: Mon Jun 02 2003 - 00:56:59 PDT
Dear SV chairs, Champions and all SV members,
Congratulations for the SystemVerilog 3.1 announcement. Thanks for your
efforts and work to develop such a magnificent system design and
verification language.
I'd request you to guide me to the following :
================================================
*SystemVerilog3.1 documentation ( an introductory level) as the LRM is
so advanced.
*SystemVerilog3.1 Tutorials. (design examples, RTL coding and
Verification)full projects tutorial is so good.
*SystemVerilog 3.1 compiler and tool to practice designs with it.
*Any Materials or resources that would help me achieving mastering
SystemVerilog 3.1 from beginner to professional level.
======================================================
--FYI, I'm in to VHDL but I'm switching to SystemVerilog and I wanna
keep track with it since its new birth..
I'm so sorry for the requests but I'm a newbie who is starting his
learning curve and I'm confident that I would find guidance from the
champions of such a giant new design and verification language.
Best Regards,
Mohamed A Salem
==========================================================
On Thu, 2003-05-29 at 23:09, Vassilios.Gerousis@Infineon.Com wrote:
> Dear SV chairs, champions and all SV members,
> It is a pleasure to announce to everyone that Accellera Board has
> approved SystemVerilog 3.1 on May 29, 2003. It is not a formal Accellera
> standard where users and EDA vendors can now start building tools and
> designs using this great technology. The following companies voted against
> SystemVerilog (Cadence and Verplex). Verisity abstained.
> I want to thank everyone who worked hard in the development of this
> new standard. We will take the next few weeks to relax. We will come back in
> few weeks to discuss the next steps.
>
> Best Regards
>
> Vassilios
-- Mohamed A Salem Handasa Arabia Organization www.handasarabia.org
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