Subject: [sv-bc] Re: [sv-ec] Question: logic & reg - what is the difference?
From: Dave Rich (David.Rich@synopsys.com)
Date: Thu Jun 05 2003 - 10:52:04 PDT
Cliff,
There were a series of straw polls for SV-BC18h,i that were held at the
BC's Jan 22 face to face meeting. The minutes are at
http://www.eda.org/sv-bc/hm/att-0379/01-03-01-22_minutes.txt .
To summarize, in the beginning there was a suggestion (by Jay) to drop
'logic' altogether and give reg the same functionality as 'logic'. We
agreed that even though designs that previously produced errors
(illegal-left-hand-assignment) would now compile, this was still
backward compatible with Verilog-2001. Then there was a discussion to
keep the keyword 'logic' since making continuous assignments to a reg
seemed awkward, and removing 'reg' was not an option.
The final vote for 18h,i was recorded in
http://www.eda.org/sv-bc/hm/att-0516/02-03_02_24.txt
So it seems that I missed the table 3.1 and we should remove the extra
words "with different use rules from reg" in the entry for logic
Dave
David W. Smith wrote:
>Cliff,
>
>I seem to remember the meeting, and the vote, where it was decided that
>logic and reg where the same thing. I think you were there. It appears that
>some text in the LRM may not have been caught when BC made the change.
>
>Since this was all done in the BC I will forward it to BC for comment.
>
>Regards
>David
>
>David W. Smith
>Synopsys Scientist
>
>Synopsys, Inc.
>Synopsys Technology Park
>2025 NW Cornelius Pass Road
>Hillsboro, OR 97124
>
>Voice: 503.547.6467
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>Email: david.smith@synopsys.com
>http://www.synopsys.com
>
>
>
>-----Original Message-----
>From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Clifford
>E. Cummings
>Sent: Wednesday, June 04, 2003 3:37 PM
>To: sv-ec@eda.org
>Subject: [sv-ec] Question: logic & reg - what is the difference?
>
>
>Hi, all -
>
>I was talking to the ModelSim developers and we ran into this question:
>
>Are logic and reg the same thing? Did I miss this proposal and vote?
>
>According to table 3.1, logic has "different use rules from reg."
>
>Section 5.6 - 3rd paragraph
>
>In SystemVerilog, all variables (including reg?) can now be written either
>by one continuous assignment, or by one or more procedural statements,
>including procedural continuous assignments. It shall be an error to have
>multiple continuous assignments or a mixture of procedural and continuous
>assignments writing to the same variable. All data types can write through
>a port.
>
>So now what is the difference between a logic and a reg?
>
>Is logic 100% redundant with reg? Both must be declared.
>
>Regards - Cliff
>----------------------------------------------------
>Cliff Cummings - Sunburst Design, Inc.
>14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
>Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com /
>www.sunburst-design.com Expert Verilog, Synthesis and Verification Training
>
>
>
>
>
-- -- Dave Rich Principal Engineer, CAE, VTG Tel: 650-584-4026 Cell: 510-589-2625 DaveR@Synopsys.com
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