Subject: [sv-bc] Accellera SystemVerilog 3.1A Focus And Plans
From: Vassilios.Gerousis@Infineon.Com
Date: Thu Jun 12 2003 - 07:19:37 PDT
The SV chairs met to discuss plans to solidify the SystemVerilog standard to
ensure an efficient IEEE handoff. The SV chairs outlined an aggressive plan
for the next 9 months to develop SystemVerilog 3.1A. We will start at the
latest by July 1 and release 3.1A by DVCON 2004 as a target.
The SV Chairs have developed 3.1A plan with milestones and schedule to
implement SystemVerilog solidification. The mission of 3.1a will include
implementation and usage feedback and the completion of 3.1 development in
all areas of design, Testbench, API and Assertions.
The focus of 3.1A will address the following:
1- Incorporate feedback from EDA vendors implementation of 3.1 and usage.
This feedback is extremely important in order for us to make 3.1A the
highest quality standard ever produced by a standard organization.
2- Complete enhancements from 3.1 development: Completing the technology
donations and extensions required to make SystemVerilog a solid foundation
for HDVL.
3- Full SystemVerilog 3.1 API: Complete the API technology donation and add
full SystemVerilog 3.1 API support.
4- Enhancement based on implemented EDA tools: We expect that many EDA
vendors (more than 30) will provide implementation feedback. Also We expect
more users to give us usage feedback based on real designs in SystemVerilog.
5- SystemVerilog 3.1 debugging, tracing and coverage enhancement (e.g. new
VCD with proposals from Novas and Synopsys).
6- Support synchronization of Verilog-AMS and SCE-API with SystemVerilog:
Based on the business directive of Accellera Board, the three committees
will work together on synchronization. A combined schedule and milestones
with Verilog-AMS and SCE-API will be put as part of three committees
milestones to support such synchronization.
As most of you know, there is a lot of active development for
SystemVerilog solutions in the market. I have counted at least 20 companies
that have about 40 products in the third quarter of 2003 for SystemVerilog.
As we did with 3.0, we will offer an implementation feedback period so we
can address the industry's implementation issues. This feedback period is
substantially shorter than that for 3.0 but we think the industry can
respond in this shorter period of time.
Based on this, the SystemVerilog Basic Committee, will immediately
become SystemVerilog Design Committee. Every topic that is a "design
modeling" related, should be routed under sv-bc. This include refinements of
the language, fixing issues as well as handling design enhancements.
Based on multiple request from several members, we will create a new
committee to explore and develop "accelerated" SystemVerilog 3.1 Testbench
(Axis, Mentor, Synopsys, Motorola, FTL, etc.). Also based on requests from
the board we will create a new committee to explore and develop a
SystemVerilog 3.1 validation suite. More detailed announcement will follow
in the next few months.
We have put together a detailed plan and mission focus for each
committee. This will be discussed in detailed by each committee. We have
added few ground rules in order to manage this new release. We will also
build a bug tracking system to help us manage 3.1A development.
Thanks for making SystemVerilog 3.1 successful. let us now focus on
the solidification through the development of SystemVerilog 3.1A. We request
all implementation and usage feedback to be sent directly to one specific
committee in the areas of (Design, Testbench, Assertion and API).
Best Regards
Vassilios
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