Subject: Re: [sv-bc] Separate Compilation Meeting Monday 6/9/03
From: Randy Misustin (ram@model.com)
Date: Wed Jun 18 2003 - 22:17:45 PDT
Hi Jay,
Jay Lawrence wrote:
>I agree with Kevin and Adam in that I don't see a difference between a
>namespace and top-level module. The interesting part of this proposal is
>the 'import' statement that allows visibility without an explicit
>hierarchical name.
>
>
I just answered Adam's mail with my view of the difference. You're
correct that 'import' is the business end of this issue. The
desirability/need for namespace stems from what an import should be
targeted.
>It appears that to do this in Verilog however, you would have to add the
>concept of order of compilation and dependancies between modules. Even
>for a guy with a VHDL background like me, this is a really really scary
>addition to Verilog. For instance, what is the requirements on search
>order when someone uses a -y/-v command line switch or `uselib to bring
>in a whole library?
>
>
This same problem exists in a much more fractured sense with the same
declarations existing in $root instead of a namespace. Similarly, this
same problem exists if you put the declarations in a module at the
toplevel and reference them hierarchically. That said, I really
appreciate you drawing attention to this whole issue of the tradeoff
between structured order of analysis/compilation and the ability of the
compiler to generate sensible messages earlier in the process. This has
long been a problem in Verilog and looks to be getting worse if it's not
addressed.
-randy.
>The other choice of course is to not require validation of the import at
>compile time and defer it to elaboration. This would mean that any
>module that has an 'import' could have any names in it and you wouldn't
>produce an error until elaboration.
>
>Jay
>
>===================================
>Jay Lawrence
>Senior Architect
>Functional Verification
>Cadence Design Systems, Inc.
>(978) 262-6294
>lawrence@cadence.com
>===================================
>
>
>
>>-----Original Message-----
>>From: Kevin Cameron [mailto:sv-xx@grfx.com]
>>Sent: Wednesday, June 18, 2003 1:29 PM
>>To: sv-bc@eda.org
>>Cc: ram@model.com; krolnik@lsil.com
>>Subject: Re: [sv-bc] Separate Compilation Meeting Monday 6/9/03
>>
>>
>>
>>
>>>From: Adam Krolnik <krolnik@lsil.com>
>>>
>>>Hi Randy;
>>>
>>>On the surface, namespaces look like modules. It may be
>>>
>>>
>>helpful in analyzing
>>
>>
>>>this to see a comparison between modules and namespaces.
>>>
>>>
>>Good point. What is the difference between nesting in a
>>module and nesting
>>in a namespace? - personally I didn't think the module
>>nesting was particularly
>>functional, maybe if you add the namespace semantics it will
>>work sensibly
>>[without anther keyword :-) ].
>>
>>
>>
>>>You also write that import statements outside a module or
>>>
>>>
>>scope will affect subsequent
>>
>>
>>>module or interface scopes.
>>>
>>>Do import statements only have file scope? Or could one
>>>
>>>
>>import something for the first
>>
>>
>>>file and have subsequent files obtain the effects of the import?
>>>
>>>I presume they have file scope. Thus for files with
>>>
>>>
>>multiple modules one import is
>>
>>
>>>sufficient.
>>>
>>>For the import statement, why would it be necessary to say
>>>
>>>import Myspace.*;
>>>
>>>Other languages (such as Perl) only require reference to
>>>
>>>
>>the name to import all
>>
>>
>>>the definitions:
>>>
>>>use Getopt::Long; # Get all definitions
>>>
>>>import Complex; // Get all verilog complex math functions.
>>>
>>>
>>An import statement in Perl would cause the interpreter to go
>>find the module
>>and load it - what's the implication for SV? - are you
>>assuming the namespace
>>is already defined (in a header)?
>>
>>Kev.
>>
>>
>>
>>>Can one import a wire/net declared in the namespace? What
>>>
>>>
>>does this mean? a wire
>>
>>
>>>that is shared by all modules importing it? What does it
>>>
>>>
>>mean if you import a
>>
>>
>>>wire but are not in a module scope? in a named scope?
>>>
>>>
>>> Thanks.
>>>
>>> Adam Krolnik
>>> Verification Mgr.
>>> LSI Logic Corp.
>>> Plano TX. 75074
>>>
>>>
>>>
>
>
>
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