Subject: Re: [sv-bc] Minutes for 7/7/03 SV-BC Meeting
From: Michael McNamara (mac@verisity.com)
Date: Wed Jul 09 2003 - 08:46:11 PDT
Dave Rich writes:
> Actually, I did find the wording in section 12.4 of 1364-2001, second
> paragraph
>
> "At the top of the name hierarchy are the names of one or more root
> modules of which no instances have been created. This root or these
> parallel root modules make up one or more hierarchies in a design
> description or description."
And indeed, in Section 12.4 of 1364-1995 the language was:
At the top of the name hierarchy are the names of modules of which
no instances have been created. It is the <i>root</i> of the
hierarchy. Inside any module, each module instance, task definition,
function definition and named begin-end or fork-join block shall
define a new branch of the hierarchy.
In the Verilog 1.1a (March 1987) manual, it said (in section 12.6)
At the top of the hierarchy are the names of modules of which no
instances have been created. Inside these free standing modules,
each module instance, task definition, function definition and named
begin-end or fork-join block defines a new name hierarchy.
What seems to be new is the '$root' name; what is old is the
possibility of multiple top level modules.
> Karen Pieper wrote:
>
> > Verilog 2K does have implicit instantiation at the $root level
> > creating top-level modules. We believe there must be language in
> > the V2K spec indicating that the implicit name for those modules
> > is the same as the module name. There is another issue that
> > addresses implicit instantiation of modules declared within other
> > modules.
> >
> > K
> >
> > At 01:12 PM 7/8/03 +0300, you wrote:
> >
> >> Regarding "11. Is there wording on the Verilog 2K spec for this?":
> >>
> >> I don't understand the question. The feature does not exist in
> >> 1364-2001, so there is no wording on it.
> >>
> >> Shalom
> >>
> >>
> >>
> >> "Karen L. Pieper" wrote:
> >>
> >> > Hi, all,
> >> >
> >> > The minutes for the 7/7/03 meeting have been posted to the sv-bc
> >> website.
> >> >
> >> > http://www.eda.org/sv-bc/minutes
> >> >
> >> > K
> >>
> >> --
> >> Shalom Bresticker
> >> Shalom.Bresticker@motorola.com
> >> Design & Reuse Methodology Tel: +972 9
> >> 9522268
> >> Motorola Semiconductor Israel, Ltd. Fax: +972 9
> >> 9522890
> >> POB 2208, Herzlia 46120, ISRAEL Cell: +972 50
> >> 441478
> >
> >
> >
> >
>
> --
> --
> Dave Rich
> Principal Engineer, CAE, VTG
> Tel: 650-584-4026
> Cell: 510-589-2625
> DaveR@Synopsys.com
>
>
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