Subject: [sv-bc] Scheduling Region Questions and Problems of new SystemVerilog commands
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Mon Jul 21 2003 - 05:16:50 PDT
Subject: Scheduling Region Questions and Problems of new SystemVerilog commands
Hi, All -
I have read and re-read sections 14-17 of the SystemVerilog 3.1 Standard
multiple times and am still
confused about exactly when events are scheduled. I think part of the
problem is that some of the
descriptions apply to program variables and other descriptions apply to
RTL-design signals (and the
distinction between the two is not well delineated).
I have attached a document showing the sections in question, typos,
questions and proposals.
I need committee members to tell me if I have correctly interpreted the 3.1
LRM.
I think this belongs mostly to the SV-EC (testbench constructs) but it may
overlap into the SV-BC (existing 1364-2001 event queues - copied) and SV-AC
(assertion sampling and scheduling - copied).
Regards - Cliff
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, Synthesis and Verification Training
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