[sv-bc] Partial proposal for SV-BC Issue 55: Attributes are missing from a few places

Subject: [sv-bc] Partial proposal for SV-BC Issue 55: Attributes are missing from a few places
From: Jacobi, Dan (dan.jacobi@intel.com)
Date: Tue Aug 05 2003 - 07:38:14 PDT

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MOTIVATION

==========

Enable the use of attributes on modport port declarations as in the
following example

interface i2;

wire a, b, c, d;

modport master ( (* att1 *) input a, b, (* att2 *) output c, d);

modport slave ( (* att3 *) output a, b, (* att4 *) input c, d);

endinerface

Adding attributes to other constructs added in SV 3.1 is not approached
in this proposal.

PROPSAL

========

* Under A.2.9

REPLACE

modport_ports_declaration ::=

modport_simple_ports_declaration

| modport_hierarchical_ports_declaration

| modport_tf_ports_declaration

WITH

modport_ports_declaration ::=

{ attribute_instance } modport_simple_ports_declaration

{ attribute_instance } | modport_hierarchical_ports_declaration

{ attribute_instance } | modport_tf_ports_declaration

Note that no changes in the language are needed - attributes for new
System-Verilog construct are mentioned in section 6.1.

Dan Jacobi

Intel Corporation

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