Subject: [sv-bc] RE: [sv-ec] SystemVerilog 3.1A Face to Face Meeting on September 18 starting at 9:00
From: Jay Lawrence (lawrence@cadence.com)
Date: Fri Aug 15 2003 - 10:39:41 PDT
I will be attending in person please save me a seat.
Jay
===================================
Jay Lawrence
Senior Architect
Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================
> -----Original Message-----
> From: Vassilios.Gerousis@Infineon.Com
> [mailto:Vassilios.Gerousis@Infineon.Com]
> Sent: Friday, August 15, 2003 5:24 AM
> To: sv-ac@eda.org; sv-bc@eda.org; sv-cc@eda.org; sv-ec@eda.org
> Subject: [sv-ec] SystemVerilog 3.1A Face to Face Meeting on
> September 18 starting at 9:00
> Importance: High
>
>
> Hi SystemVerilog Members,
> We will have a face to face meeting in San Jose area on
> September
> 18. The meeting will have a limited seating. So please RSVP
> to save a seat
> for you. The topics to be discussed in this meeting are:
>
> a- Status of each SV committee.
> b- Presentation on donations.
> c- Status for LRM Errata.
> d- Status of separate compile.
> d- A kick meeting to discuss the technology aspects of SV Testbench
> acceleration. If the results are promising, we may create
> another committee
> to address such a capability.
>
> A more detailed agenda, place for the meeting and conference
> call will be
> sent soon.
>
> Best Regards
>
> Vassilios
>
>
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