Subject: [sv-bc] Terms and Conditions of Use of Accellera Standards
From: Vassilios.Gerousis@Infineon.Com
Date: Mon Sep 15 2003 - 00:18:27 PDT
Dear SystemVerilog Members,
Based on multiple requests by several EDA companies, IP companies
and users, Accellera has developed the terms and conditions to be applied to
all of its standards. It is important to emphasize that this has been
Accellera policy from day one. We just putting this in words for everyone to
see. It allows anyone the freedom to use and implement any IP without a
license as long the conditions in the use have been applied. Accellera
officers, Accellera Lawyer and the few of the technical chairs have
developed the final wording of such terms and conditions. In few days, this
will become an official statement pending few approvals. This re-affirms
Accellera commitment to provide excellent quality standards available to all
for implementation, usage and commercial application.
Best Regards
Vassilios
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Agreement Concerning Terms and Conditions of Use of Accellera's
SystemVerilog Standard
This User Agreement governs the terms and conditions of use that apply to
Accellera's SystemVerilog standard.
Proprietary Rights
Accellera's SystemVerilog is owned and copyrighted exclusively by the
Accellera Organization, Inc. Our SystemVerilog standard contains copyrighted
material, trademarks and other proprietary information, including text,
software, and graphics, and the entire content of Accellera's SystemVerilog
is copyrighted as a collective work under the United States copyright laws.
Accellera also owns a copyright in the selection, coordination, arrangement
and enhancement of such content, as well as in the content original to it.
You cannot use any aspect of Accellera's SystemVerilog unless you have
accepted this User Agreement. By accessing our SystemVerilog or any of its
content, in whatever form, you affirmatively acknowledge Accellera's
proprietary rights in our SystemVerilog and all its content and
affirmatively agree to accept the terms and conditions of use set forth in
this User Agreement or any amendment thereof. Each time you use our
SystemVerilog or any of its content, in whatever form, you reaffirm your
acknowledgment of Accellera's proprietary rights and your acceptance of the
then-current User Agreement.
If you do not wish to be bound by the User Agreement, you may not access,
use or continue to use our SystemVerilog or any of its content. Accellera
may change the terms and conditions of this User Agreement from time to time
as we see fit and in our sole discretion. Such changes will be effective
immediately upon posting, and you agree to the new posted changes by
continuing your access to or use of our SystemVerilog or any of its content
in whatever form.
Accellera's License to You
The purpose of the following license is to promote the world-wide acceptance
of the language-based electronic design standards approved by Accellera.
Accellera, therefore, grants you a non-exclusive, limited license to access
and use our SystemVerilog, in accordance with this User Agreement, for the
implementation, use and/or study of Accellera's approved electronic design
standards in connection with your commercial, scientific, educational and
related activities.
Except as expressly provided in the license granted above concerning
Accellera's approved electronic standards, or as otherwise expressly
permitted under copyright law, you may not copy, redistribute, publish,
create derivative works from, sub-license or charge others to access or use,
participate in the transfer or sale of, or directly or indirectly
commercially exploit Accellera's SystemVerilog or any of its content without
first obtaining Accellera's express, written permission.
Indemnification
You agree to defend, indemnify and hold harmless Accellera and their
directors, officers, employees and agents from and against all claims and
expenses, including attorneys' fees, arising out of your use of Accellera's
SystemVerilog.
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