Subject: [sv-bc] logic -vs- ulogic - user input
From: Karen Pieper (Karen.Pieper@synopsys.com)
Date: Mon Sep 22 2003 - 08:53:10 PDT
I'm forwarding the following bounced email.
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>From: Dan Ciobanu <dciobanu@comcast.net>
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>Subject: logic -vs- ulogic - user input
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>Hello,
>
>I did read Cliff Cummungs' email regarding the above subject, posted on
>comp.lan.verilog.
>I'm mostly a VHDL user for the last 10 years and I agree with Cliff that
>you should change
>the type logic to ulogic, because it behaves like the VHDL std_ulogic,
>i.e. has no resolution function.
>
>The most dangerous and hard to detect bugs are generated by
>misunderstanding the semantic of a type.
>Keeping the type name logic but without a resolution function will
>confuse the VHDL users and will create
>big problems for Verilog users who not used with a strongly typed
>language, overloading and resolution functions.
>Far too many designed are mixed-language today to allow such a semantic
>ambiguity to exist in SystemVerilog.
>
>Regards,
>Dan
>
>Dan Ciobanu
>Snr. Staff Engineer
>Maxtor Corp.
>Milpitas CA
>
>Disclaimer: These are my personal opinions and do not represent in any
>way my employer's view
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