Subject: Re: [sv-bc] Proposals for SV3.1a
From: Adam Krolnik (krolnik@lsil.com)
Date: Tue Sep 23 2003 - 11:37:26 PDT
HI Dave;
Thanks for the explanation.
You wrote two reasons:
>1. to be able to represent hardware as a function call, and later replace the call
with >the actual hardware, without have to change the function call.
What about components with multiple outputs? How does this address the needs
of a full adder, a 4-2 adder, etc?
>2. to represent hardware as a function call and not need to create names for all the
>top level interconnect signals.
I am going to hate to debug any netlists that cascade function calls within function
calls. No net names to see, no instance names to key off of, etc.
I can see that this simplifies a code generator's work. A user might make some use
of this as well. But I do not see this as a complete robust solution. People would
most likely have to change structures if they needed: another output, or more
information for debugging...
Thanks Dave.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
Co-author "Assertion Based Design"
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