Subject: Re: [sv-bc] SV-BC 14 non-local typedefs.
From: Greg Jaxon (Greg.Jaxon@synopsys.com)
Date: Mon Oct 13 2003 - 01:28:16 PDT
Dave,
Could you comment on how this proposal relates to the following section 7.14 text?
"Unpacked structures types are equivalent by the hierarchical name of its type alone.
This means in order to have two equivalent unpacked structures in two different scopes,
the type must be defined in one of the following ways:
— Defined in a higher-level scope common to both expressions.
— Passed through type parameter.
— Imported by hierarchical reference."
Is it the case that only a typedef statement can import a type, and that
doing this will not cause the creation of a distinct type due to its new
"hierarchical name"?
Greg Jaxon
Dave Rich wrote:
> The following section is being replaced to make it clear that hierarchical
> references to types are not allowed.
>
> Replace the following in section 3.9 User defined types
> vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
> If the type is defined within an interface, it must be re-defined locally before
> being used.
>
> interface it;
> typedef int intP;
> endinterface
> it it1 ();
> typedef it1.intP intP;
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> with
> vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
> User defined type identifiers have the same scoping rules as data identifiers,
> except that hierarchical reference to type identifiers shall not be allowed.
> References to type identifiers defined within an interfaces through ports are
> allowed provided they are locally re-defined before being used.
>
> *interface *intf_i;
> *typedef int *data_t;*
> endinterface
>
> module *sub(intf_i_i p)*
> typedef *p.data_t my_data_t;
> my_data_t data; //type of 'data'' will be int when connected to interface above*
> endmodule*
>
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> Note: keywords in example above are bold.
>
>
> --
> --
> David.Rich@Synopsys.com
> Technical Marketing Consultant
> http://www.SystemVerilog.org
> tele: 650-584-4026
> cell: 510-589-2625
>
>
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