Re: [sv-bc] Non-member submission from [Andy Tsay <andytsay@yahoo.com>]

Subject: Re: [sv-bc] Non-member submission from [Andy Tsay ]
From: Dave Rich (David.Rich@synopsys.com)
Date: Tue Oct 21 2003 - 23:39:49 PDT

Andy,

See my interpretation below. Most of this information comes from Section
4.4 of the 1364-2001 spec.

Dave

Vassilios.Gerousis@Infineon.Com wrote:

>Forwarded for Andy Tsay.
>
>================================================================
>Hi,
>
>>From SV 3.1 LRM, section 2.3:
>SystemVerilog adds the ability to specify unsized literal single bit values
>with a preceding apostrophe ( ' ), but without the base specifier. All bits
>of the unsized value are set to the value of the specified bit. In a
>self-determined context these literals have a width of 1 bit, and the value
>is treated as unsigned.
>
>Can someone help to clarify if the following
>examples are interpreted correctly?
>
>1) wire [3:0] a = '1; // a = 4'b1111 -- all 4 bits set to 1'b1
>
Correct

>2) wire [3:0] b = a + '1; // b =(a + 4'b1111) -- all 4 bits set to 1'b1
>
Correct.

>3) wire [3:0] c = {`1,`1,`1}; // c = 4'b0111 -- self-determined '1 is 1'b1
>
Illegal. Section 4.1.14 of 1364-2001 "Unsized constant numbers shall not
be allowed in concatenations" I think rule this takes precedence over
self-determination since unsized constant numbers can be used in
self-determined contexts.

>4) if (a == '1) // if (a == 4'b1111)
>
Correct

>5) wire [3:0] d = (a[3] == '1)?b:c; // (a[3] == 1'b1)?b:c
>
Correct

>6) bit [3:0] val;
> case ('1)
> a[3:0]: val = 4'b1111; // if (a[3:0] == 4'b1111) val = 4'b1111;
> a[3:1]: val = 4'b1110; // else if (a[3:1] == 3'b111) val = 4'b1110;
> a[3:2]: val = 4'b1100; // else if (a[3:2] == 2'b11) val = 4'b1100;
> a[3:3]: val = 4'b1000; // else if (a[3:3] == 1'b1) val = 4'b1000;
> default val = 4'b0000; // else val = 4'b0000;
> endcase
>
Incorrect.. Section 9.5 of 1364-2001 "The length of all the case item
expressions, as well as the case expression in the parentheses, shall be
made equal to the length of the longest case expression and case item
expression." Thus all will be compared to 4'b1111

>
>Thanks,
>Andy Tsay
>
>
>
> 

-- 
--
David.Rich@Synopsys.com
Technical Marketing Consultant
http://www.SystemVerilog.org
tele:  650-584-4026
cell:  510-589-2625

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