Subject: [sv-bc] A question about interfaces and modports
From: Jacobi, Dan (dan.jacobi@intel.com)
Date: Thu Oct 23 2003 - 07:05:56 PDT
The system Verilog LRM clearly specifies that if no modport is used in
the model header or in the port connections then, all the nets and
variables in the interface are accessible and will receive a direction
of an inout or a ref (proposed to change to inputs). This enabled us to
use interfaces with out declaring modports.
However me any my colleagues were debating the following issue:
Lets assume we have an interface and only part of it's variables and
nets are members of a specific modport declared in this interface such
as the following RTL:
interface i1();
reg r1,r2;
wire w1,w2;
modport master (input r1,w1);
modport slave (output w1,r1, input r2,w2);
endinterface : i1
Then we use that modport as a port in a declared module
module top();
i1 myint();
son s1(myint);
...
endmodule
module son (myint.master p1);
...
endmodule
The question is, are the variables and nets that were not declared as
part of the modport accessible by the
module using that modport ? if they are what is the direction of these
signals.
Or in a more high level aspect, is the modport used only to define a set
of directions of the interface's signals when the interface is used as a
modules port, or is the modport used to specify which signals should be
connected to the module ?
Back to my RTL - In the model son can we access the signals p1.r2 and
p1.w2 ? If we can what are the corresponding directions ?
Should we add some language that clarifies this issue
Thanks
Dan Jacobi
Intel Corp
INet : 465-5855
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