Subject: [sv-bc] Issues about unpacked structure and array type assignment compatibility
From: Francoise Martinolle (fm@cadence.com)
Date: Mon Oct 27 2003 - 11:59:54 PST
I am finding possibly conflicting or unclear statements in the 3.1 LRM
regarding unpacked types assignment compatibility.
In section 11.25: I found:
2) SystemVerilog structs are type compatible so long as their bit sizes are
the same, thus copying structs of
different composition but equal sizes is allowed. In contrast,
SystemVerilog objects are strictly strongly typed.
Copying an object of one type onto an object of another is not allowed.
Note: is the bit size of an unpacked structure defined? Or is this clause
(2) only pertaining to packed structs (essentially vectors).
And In section 7.14 (aggregate expressions ) I found:
7.14 Aggregate expressions
Unpacked structure and array variables, literals, and expressions can all
be used as aggregate expressions. A
multi-element slice of an unpacked array can also be used as an aggregate
expression.
Aggregate expressions can be copied in an assignment, through a port, or as
an argument to a task or function.
Aggregate expressions can also be compared with equality or inequality
operators. To be copied or compared,
the type of an aggregate expression must be equivalent.
Unpacked structures types are equivalent by the hierarchical name of its
type alone. This means in order to
have two equivalent unpacked structures in two different scopes, the type
must be defined in one of the following
ways:
— Defined in a higher-level scope common to both expressions.
— Passed through type parameter.
— Imported by hierarchical reference.
Unpacked arrays types are equivalent by having equivalent element types and
identical shape. Shape is defined
as the number of dimensions and the number of elements in each dimension,
not the actual range of the dimension.
The later seems to specify that a variable of an unpacked struct can only
be assigned to another variable of the SAME struct type.
It only says that a variable of an array type can be assignment to another
variable of an array type which has the SAME element type, same number of
dimensions and same width for each dimension.
Therefore I could not assign an array of reals to an array of integers
because their element type is not equivalent. I am also guessing that type
equivalence means same type but not the same type name. Type equivalence
should be defined in SystemVerilog LRM.
In summary I see several issues:
section 11.25: what is the bit size of a structure? Sentence needs to be
clarified
section 11.14: what is type equivalence? It is not defined anywhere.
why would the rule for structure copy or comparison
require that they have the same type? Why not just requiring that struct
variables have struct types of the same shape but not the same name?
typedef struct {
int a, b;
} struct1
typedef struct {
int x, y;
} struct2.
struct1 var1;
struct2 var2;
initial
var1 = var2; // is this legal?
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