Subject: Re: [sv-bc] Issues about unpacked structure and array type assignment compatibility
From: Francoise Martinolle (fm@cadence.com)
Date: Tue Oct 28 2003 - 09:18:15 PST
Thanks Greg,
One more question.
Is it allow to have a structure concatenation assigned to a packed struct?
Ex;
typedef struct {
int a, b;
} struct1;
struct1 var1 = {a : 0, b : 2};
I don't think it should as it would cause ambiguity with positional
associations which is
undistinguishable from normal old Verilog concatenations.
The result could be different depending if you would interpret it as an old
concatenation or as a structure concatenation.
Ex:
typedef packed struct {
logic [1:0] a;
logic b;
} struct1; This is a 3 bit vector
struct1 var1 = {2'b00, 3'b100}; This is an old verilog concatenation which
result is a 5 bit truncated to the 3 bits when assigned to the left hand
side. var1 should be assigned 3'b100.
If this is considered as a structure concatenation, then the assignments
(extension and truncation ) are made per field and the result of var1 would
be 3'b000.
Francoise
'
>>typedef struct {
>> int a, b;
>>} struct1
>>typedef struct {
>> int x, y;
>>} struct2.
>>struct1 var1;
>>struct2 var2;
>>initial
>> var1 = var2; // is this legal?
>
>No.
>
>
>Greg Jaxon
>
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