[sv-bc] SystemVerilog 3.1a Draft 1


Subject: [sv-bc] SystemVerilog 3.1a Draft 1
From: David W. Smith (David.Smith@synopsys.com)
Date: Wed Oct 29 2003 - 14:20:14 PST


Greetings,

The first draft of SystemVerilog 3.1a is now available at http://www.eda.org/sv/SystemVerilog_3.1a_draft1.pdf.

It is listed on the home page for www.eda.org/sv under working documents.

Stu had done his normally wonderful job of collecting all of the work from all four committees into a single document. Also notice that he has put the new SystemVerilog logo on the front page. Cool! (higher resolution version on the next draft).

I have also updated the SV site to now separate all the new changes that will be made into Draft 2 changes. All changes must now be based on Draft 1 (for text, numbering, etc...).

Regards
David



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