RE: [sv-bc] Need help on "library file_path syntax"

Subject: RE: [sv-bc] Need help on "library file_path syntax"
From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Fri Oct 31 2003 - 12:24:35 PST

There are no <> in the include_statement either --

    http://www.boyd.com/1364_btf/report/full_pr/462.html

    http://www.eda.org/sv-bc/hm/att-1100/01-BNF_reconciliation2.htm

-- Brad

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of Andy
Tsay
Sent: Friday, October 31, 2003 11:41 AM
To: Steven Sharp; krolnik@lsil.com
Cc: sv-bc@eda.org
Subject: Re: [sv-bc] Need help on "library file_path syntax"

Hi,

Thanks for the inputs.
The examples on page 201 (IEEE 1364-2001 LRM) show uses of // comments.

Also the same LRM, Section 13.2.2 third paragraph says:
The syntax of a lib.map file is limited to library specifications, include
statements, and standard Verilog comment syntax.

So, standard Verilog comment syntax is allowed in a lib.map file, and
reverting SV to Vlog-2001 does not seem to help in the solution.

Can we enhace library_declaration syntax by adding <> around the
file_path_spec?
This will also be consistent with the syntax of include_statement.

Original Syntax:
  library_declaration ::=
    library library_identifier file_path_spec [ { , file_path_spec } ]
    [ -incdir file_path_spec [ { , file_path_spec } ] ;
  include_statement ::=
    include <file_path_spec> ;
Proposed Syntax:
  library_declaration ::=
    library library_identifier <file_path_spec> [ { , <file_path_spec> } ]
    [ -incdir <file_path_spec> [ { , <file_path_spec> } ] ;
  include_statement ::=
    include <file_path_spec> ;

Thanks,
Andy

--- Steven Sharp <sharp@cadence.com> wrote:
> I believe that SV is allowing library mapping to be specified in the
Verilog
> source. And since Verilog source can have comments, that leads to this
> problem.
>
> I think that allowing library mapping in the Verilog source is going in
the
> wrong direction. The IEEE VSG is considering going the other direction,
and
> only allowing configs in the lib.map file, not the Verilog source.
>
> Steven Sharp
> sharp@cadence.com
>

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