Subject: [sv-bc] left/right justified and patched with zero
From: Andy Tsay (andytsay@yahoo.com)
Date: Mon Nov 03 2003 - 16:14:02 PST
Hi,
In SV3.1a draft 1 LRM:
A string literal can be assigned to a character, or a packed array, as in
Verilog-2001. If the size differs, it is right justified.
byte c1 = "A" ; bit [7:0] d = "\n" ;
bit [0:11] [7:0] c2 = "hello world\n" ;
A string literal can be assigned to an unpacked array of characters, and a zero
termination is added like in C. If the size differs, it is left justified.
byte c3 [0:12] = "hello world\n" ;
QUESTION:
If there are more elements than the string literal can take, does the LRM
specifies to fill the rest of the elements to '0 value?
For examples:
byte unpk[0:13] = "hello world\n";
// same as unpk = {"hello world\n",8'b0, 8'b0}; ???
byte [0:13] pk = "hello world\n";
// same as pk = {8'b0, 8'b0,"hello world\n"}; ???
Thanks,
Andy
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