Subject: Re: [sv-bc] left/right justified and patched with zero
From: Greg Jaxon (Greg.Jaxon@synopsys.com)
Date: Wed Nov 12 2003 - 10:30:24 PST
The "problem" is the (widespread?) use of fixed-size data type names
followed by (packed) dimension brackets which are currently ignored.
Using "typedef" to indicate that the System Verilog definition is desired
might work, but it relies on two shaky facts:
1) The typedef statement could contain both the fixed-size data
typename and the packed dimension. In this case, the LRM
has to point out that the typedef differs from the analogous
data declaration. Programs converted from non-standard Verilog
to System Verilog may run afoul of this if they naively edit
declaration syntax into typedefs without checking for this
semantic shift.
2) The typedef could contain just the fixed-size data typename.
The packed dimensions being added later in a data declaration or
second typedef. This case is more likely to be expecting
System Verilog's definition, because the type identifier expresses
separation of concerns about the element type from concerns
about the packed array structure. However the shaky fact here
is whether any of the other type-equivalence rules make a
distinction between the typedef name and its definition. Dave
does not expect to see the typedef levels become part of the
type-signature, and he expects to use the type-equivalence relationship
to decide whether a packed dimension can apply to the given type.
I've noted several times that type-equivalence for packed data is not
well-defined in the LRM yet. Whomever is composing that section should
consider incorporating the rules about typedef levels in type signatures.
I think Peter's proposal delivers the most useful definition of typedefs
and type parameters. It has this glitch regarding fixed-size data types.
My suggestion to Dave is to take any fixed-size type that appears inside
a typedef or type parameter and immediately coerce it to its bit or logic
(signed) packed vector representation.
Greg
Peter Flake wrote:
> Dave,
>
> Using a typedef removes the problem because there is no backwards
> compatibility issue, since Verilog does not have typedefs.
>
> Peter.
>
> At 17:35 05/11/2003 -0800, Dave Rich wrote:
>
>> Andy,
>>
>> First thing I want to say is that SV3.1 now has string data types, so
>> dealing with characters at the bit level is no longer needed.
>>
>> Second, the reason fixed-sized data types like byte and int are not
>> legal has to do with the fact that some Verilog95/2001 simulators
>> allow you to declare fixed sized data types with a range and then
>> ignore the range, which is non standard behavior. This type of coding
>> is prevalent enough that if we allowed packed arrays of fixed sized
>> data types, we would break existing code. See earlier emails on the
>> reflector that deal with this issue.
>>
>> Using a typedef does not remove the problem.
>>
>> Dave
>>
>>
>> Andy Tsay wrote:
>>
>>> Hi,
>>>
>>> Thanks for the clarifications that
>>> 1. Illegal: byte [0:13] pk = "hello world\n";
>>> 2. Legal, right justified: bit [0:13][0:7] pk = "hello world\n";
>>> Both pk[0] and pk[1] are filled with 0.
>>> 3. Legal, left justified: byte unpk [0:13] = "hello world\n";
>>> Both unpk[12] and unpk[13] are filled with 0.
>>>
>>> Shall we consider to make case 1 legal?
>>> If the follwong is legal, how to fill data to pk2?
>>> typedef byte BYTE; // make BYTE a type_declaration_identifier
>>> BYTE [0:13] pk2 = "hello world\n"; // type_decl_id packed_dimension
>>>
>>> Thanks,
>>> Andy
>>>
>>>
>>> --- Arturo Salz <Arturo.Salz@synopsys.com> wrote:
>>>
>>>
>>>> My apologies. Keith is correct.
>>>>
>>>> Arturo
>>>>
>>>> ----- Original Message -----
>>>> From: "Gover, Keith" <keithg@model.com>
>>>> To: "Gover, Keith" <keithg@model.com>; "'Arturo Salz'"
>>>> <Arturo.Salz@synopsys.COM>; "Andy Tsay"
>>>> <andytsay@yahoo.com>; "Greg Jaxon" <Greg.Jaxon@synopsys.COM>
>>>> Cc: <sv-bc@eda.org>
>>>> Sent: Wednesday, November 05, 2003 12:43 AM
>>>> Subject: RE: [sv-bc] left/right justified and patched with zero
>>>>
>>>>
>>>> Oops ... wrong cut and paste. Should have been the unpacked array:
>>>>
>>>> byte unpk[0:13] = "hello world\n";
>>>>
>>>> -Keith
>>>>
>>>> --------------------------------------------------------
>>>> -- Keith Gover
>>>> -- Technical Marketing Engineer
>>>> -- Model Technology, Inc.
>>>> -- office: (503) 685-0896
>>>> -- mobile: (503) 703-2476
>>>> -- email: keithg@model.com
>>>> --------------------------------------------------------
>>>> ------- __@ __@ __@ __@ __~@
>>>> ----- _`\<,_ _`\<,_ _`\<,_ _`\<,_ _`\<,_
>>>> ---- (*)/ (*) (*)/ (*) (*)/ (*) (*)/ (*) (*)/ (*)
>>>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>>> "The Only Easy Day was Yesterday!"
>>>>
>>>> -----Original Message-----
>>>> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of
>>>> Gover, Keith
>>>> Sent: Wednesday, November 05, 2003 5:40 PM
>>>> To: 'Arturo Salz'; Andy Tsay; Greg Jaxon
>>>> Cc: sv-bc@eda.org
>>>> Subject: RE: [sv-bc] left/right justified and patched with zero
>>>>
>>>>
>>>> Hi Arturo,
>>>>
>>>> I think your statement about assignments to unpacked arrays
>>>> conflicts with
>>>> what is stated in section
>>>> 2.6. It states:
>>>>
>>>> A string literal can be assigned to an unpacked array of characters,
>>>> and a zero termination is added like in C. If the size differs, it
>>>> is left justified.
>>>>
>>>> byte c3 [0:12] = "hello world\n" ;
>>>>
>>>> Therefore the assignment in Andy's example should be legal:
>>>>
>>>> byte [0:13] pk = "hello world\n";
>>>>
>>>> -Keith
>>>>
>>>> --------------------------------------------------------
>>>> -- Keith Gover
>>>> -- Technical Marketing Engineer
>>>> -- Model Technology, Inc.
>>>> -- office: (503) 685-0896
>>>> -- mobile: (503) 703-2476
>>>> -- email: keithg@model.com
>>>> --------------------------------------------------------
>>>> ------- __@ __@ __@ __@ __~@
>>>> ----- _`\<,_ _`\<,_ _`\<,_ _`\<,_ _`\<,_
>>>> ---- (*)/ (*) (*)/ (*) (*)/ (*) (*)/ (*) (*)/ (*)
>>>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>>> "The Only Easy Day was Yesterday!"
>>>>
>>>> -----Original Message-----
>>>> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of
>>>> Arturo Salz
>>>> Sent: Wednesday, November 05, 2003 5:16 PM
>>>> To: Andy Tsay; Greg Jaxon
>>>> Cc: sv-bc@eda.org
>>>> Subject: Re: [sv-bc] left/right justified and patched with zero
>>>>
>>>>
>>>> Andy,
>>>>
>>>> The declaration "byte [0:13] pk " is illegal.
>>>> Packed arrays can only be made of the single bit types (bit, logic,
>>>> reg,
>>>> wire,...).
>>>> The legal version of what I believe you want is:
>>>> bit [0:13][0:7] pk = "hello world\n";
>>>> And then
>>>> pk[0] is 0
>>>> pk[1] is 0
>>>> ...
>>>> pk[12] is "d"
>>>> pk[13] is "\n"
>>>>
>>>> The declaration "byte unpk[0:13]" is legal, but the assignment is
>>>> illegal.
>>>> You could do the following:
>>>> byte unpk[0:13] = { "h", "e", "l", "l", ... "d", 0, 0 };
>>>> But then the sizes have to match, which is why I added 0,0 at the end.
>>>>
>>>> Arturo
>>>>
>>>> ----- Original Message -----
>>>> From: "Andy Tsay" <andytsay@yahoo.com>
>>>> To: "Greg Jaxon" <Greg.Jaxon@synopsys.COM>
>>>> Cc: <sv-bc@eda.org>
>>>> Sent: Monday, November 03, 2003 5:13 PM
>>>> Subject: Re: [sv-bc] left/right justified and patched with zero
>>>>
>>>>
>>>> Hi,
>>>>
>>>> Let me try to put it in another way.
>>>> For the following examples:
>>>> byte unpk[0:13] = "hello world\n";
>>>> byte [0:13] pk = "hello world\n";
>>>>
>>>> What are the values for unpk[12], unpk[13], pk[0], and pk[1]?
>>>>
>>>> Thanks,
>>>> Andy
>>>>
>>>> --- Greg Jaxon <Greg.Jaxon@synopsys.com> wrote:
>>>>
>>>>
>>>>> Andy Tsay wrote:
>>>>>
>>>>>
>>>>>
>>>>>> byte unpk[0:13] = "hello world\n";
>>>>>> // same as unpk = {"hello world\n",8'b0, 8'b0}; ???
>>>>>>
>>>>> Please ask this in the form
>>>>>
>>>>> // same as unpk = "hello world\n\0\0"; ???
>>>>>
>>>>> Since as posed it yields a length error trying to put three things
>>>>> into
>>>>> and array of 14 things.
>>>>>
>>>>> Greg Jaxon
>>>>>
>>>>>
>>>>>
>>>>
>>>
>>>
>>>
>>
>> --
>> --
>> David.Rich@Synopsys.com
>> Technical Marketing Consultant
>> http://www.SystemVerilog.org
>> tele: 650-584-4026
>> cell: 510-589-2625
>>
>>
>
>
>
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