Subject: Re: FW: [sv-bc] task/function_declaration with empty port_list
From: Guillermo Maturana (maturana@sbcglobal.net)
Date: Wed Nov 12 2003 - 17:02:47 PST
This is not an argument in favor or against the legality of functions
with no arguments, rather feedback regarding its practical impact:
Temporal sequence and properties are allowed to be instantiated with
no arguments. While they are not functions/tasks, this feature requires
parsers to deal with a single identifier to refer to a sequence rather
than a variable within expressions.
_Matute
Brad Pierce wrote:
>It could be that the example in 11.3 is the bug. But
>it does seem reasonable to allow this, just as SystemVerilog
>allowed user-defined tasks of no arguments to be enabled
>with "t();" -- by analogy with instantiation of modules
>with no ports, which *must* use the () notation in both
>Verilog and SystemVerilog.
>
>We should make sure that this does not introduce ambiguity
>because of the interaction with named_function_proto.
>
>It's interesting that named_function_proto is less restrictive
>than named_task_proto.
>
>Also, where is the language in the LRM that allows user-defined
>functions of no arguments? This is reasonable, but it
>is illegal in Verilog.
>
>-- Brad
>
>-----Original Message-----
>From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of Karen
>Pieper
>Sent: Wednesday, November 12, 2003 2:35 PM
>To: sv-bc@eda.org
>Subject: Fwd: FW: [sv-bc] task/function_declaration with empty port_list
>
>
>
>
>
>>From: Hermann.Ilmberger@infineon.com
>>X-Authentication-Warning: server.eda.org: pieper set sender to
>>Hermann.Ilmberger@infineon.com using -f
>>To: owner-sv-bc@eda.org
>>Subject: FW: [sv-bc] task/function_declaration with empty port_list
>>Date: Wed, 12 Nov 2003 15:18:55 +0100
>>X-Message-Flag: Follow up
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>>
>>Hi,
>>I sent this to the list two days ago, but it never made it. I am member of
>>the list.
>>Best regards,
>>-Hermann
>>Hermann Ilmberger, Infineon Technologies AG
>>
>>-----Original Message-----
>>From: Ilmberger Hermann (CL DAT TDM VM)
>>Sent: Monday, November 10, 2003 3:32 PM
>>To: sv-bc@eda.org
>>Subject: [sv-bc] task/function_declaration with empty port_list
>>
>>
>>Hi,
>>
>>is this a bug in the formal syntax of SV3.1?
>>The formal syntax for function_declaration does not allow
>>
>>function juhu(); // with empty function_port_list
>>...
>>endfunction
>>
>>However, it seems that this is desirable for functions that
>>do not take arguments. Examples appear in section 11.3:
>>
>>class Packet;
>>function new();
>>...
>>endfunction
>>task clean();
>>...
>>endtask
>>endclass
>>
>>However, in 19.6.2:
>>import task slaveRead(),
>> task slaveWrite());
>>This is o.k. since named_function_proto allows an empty
>>list_of_function_proto_formals.
>>
>>Section 10.5.5 "Optional argument list" seems to refer only to
>>
>>
>function/task
>
>
>>call and
>>not to declaration.
>>
>>Cheers,
>>-Hermann
>>Hermann Ilmberger, Infineon Technologies AG
>>
>>
>
>
>
>
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