Subject: [sv-bc] Re: [sv-ec] New errata - wildcard equality
From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Mon Nov 17 2003 - 02:47:31 PST
Dave,
Assuming that you want the wild equality operators to have casez semantics, as
you say, then the following sentence,
"The =?= and !?= operators treat Z as wild cards that match any value, thus,
they will not result in X when matched with a Z value,"
is misleading. It says that because Z is a wild card, that is the reason that
the result is not X.
But that is not so. ===, !==, case, casez, and casex all never return X.
The comparison result is always True or False, never X.
The difference between them is that casez causes a Z matched with 0 or 1 to be
True instead of False.
However, I disagree that it is self-evident that "To be useful for design RTL,
the wildcard operator must propagate Xs and match casez semantics."
Consider the following:
- I anyway design with high-level constructs that do not propagate X, such as
"if-else" and "case".
- If I consider X to be "either 0 or 1", then I may want it to match them.
- I may use X in synthesizable code as "don't care".
- Even casez semantics treat X differently in RTL than in gate-level. It is
simply not true that "casez propagates X". It does treat X differently than Z.
- So even your proposal does not cause the wildcard operator to propagate X.
- Synthesizable code anyway does not enable me to deal with X.
- Bening and Foster in "Verifiable RTL" preferred casex to casez.
- Furthermore, I want the wildcard operator not just for design RTL, also for
verification and non-synthesizable design and behavioral models.
I'm not sure which is preferable, but there seems to be a mantra that "casex is
bad, casez is good".
However, I've yet to see a convincing argument for it.
Shalom
Dave Rich wrote:
> I put this as a proposal to both the EC and BC.
>
> To be useful for design RTL, the wildcard operator must propagate Xs and match
> casez semantics. The original VERA donation did not have this as a
> consideration for design.
>
> Remove the striked text in table 7-1
>
> a equals b, X and Z values act as wild cards
> a not equals b, X and Z values act as wild cards
>
> Remove the striked text in section 7.5 and add the text in blue
>
> The wild equality operator (=?=) and inequality operator (!?=) treat X and Z
> values in a given bit position as a
> wildcard.
>
> The three types of equality (and inequality) operators in SystemVerilog behave
> differently when their operands
> contain unknown values (X or Z). The == and != operators result in X if any of
> their operands contains an X or
> Z. The === and !== check the 4-state explicitly, therefore, X and Z values
> shall either match or mismatch,
> never resulting in X. The =?= and !?= operators treatX or Z as wild cards that
> match any value, thus, they too
> never will not result in X when matched with a Z value.
>
> --
> --
> David.Rich@Synopsys.com
> Technical Marketing Consultant
> http://www.SystemVerilog.org
> tele: 650-584-4026
> cell: 510-589-2625
>
>
-- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
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