Subject: Re: [sv-bc] Interface notes from Friday's meeting
From: Kevin Cameron (sv-xx@grfx.com)
Date: Tue Nov 18 2003 - 10:21:18 PST
> At 11:58 AM 11/17/03 -0800, you wrote:
> >Hi, All -
> >
..............
> >
> >Another example would be that in the Verilog language, anything on the
LHS
> >of a procedural assignment must be declared to be a variable type
> >(typically, of type reg). This is used for modeling both sequential and
> >combinational logic. There is no such concept in real hardware. (note that
> >VHDL signals are a much better representation of hardware than Verilog
> >nets and variables and VHDL engineers think the whole concept of separate
> >declarations for wires and regs to be very silly - they're right!)
VHDL's modeling of signals is broken. Due to the use of port boundary
type conversion in VHDL signal resolution is done hierarchically which NEVER
happens in real hardware. The problem (for both languages) is that the
creation of drivers for a signal is implicit rather than explicit which
leads to the confusing syntax/semantics of reg vs. wire.
I prefer the syntax of VHDL and the semantics of Verilog for hardware
modeling. Unfortunately the semantics of SystemVerilog seem to be leaning
in a VHDL direction and the syntax has become byzantine.
IMO, if syntax and semantics don't support back-annotation or plug-and-play
with analog models, it isn't a good hardware description language - and
the interface stuff doesn't appear to do either of those things.
Regards,
Kev.
.........
> >Regards - Cliff
> >
> >----------------------------------------------------
> >Clif
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