Subject: Re: [sv-bc] Need help on unique/priority if statement
From: Dave Rich (David.Rich@synopsys.com)
Date: Wed Nov 26 2003 - 14:01:28 PST
This was recently made illegal by SV-BC-70.
http://www.eda.org/sv-bc/display_issue.cgi?issue_num=70
You would now need to add begin/end around the nested if.
Dave
Andy Tsay wrote:
>Hi,
>
>Happy holidays.
>I need help for the usage examples of unique/priority if statement.
>
>SystemVerilog 3.1a, Section 8.4 Selection statements:
>
>if_else_if_statement ::=
>[ unique_priority ] if ( expression ) statement_or_null
>{ else [ unique_priority ] if ( expression ) statement_or_null }
>[ else statement_or_null ]
>
>Can someone help to explain what the priority/unique keywords do in the
>following example:
> priority if (c1)
> v1 = exp1;
> else unique if (c2)
> v1 = exp2;
> else if (c3)
> v1 = exp3;
> else unique if (c4)
> v1 = exp4;
> else priority if (c5)
> v1 = exp5;
> else
> v1 = '0;
>
>Thanks,
>Andy
>
>
>
>
-- -- David.Rich@Synopsys.com Technical Marketing Consultant http://www.SystemVerilog.org tele: 650-584-4026 cell: 510-589-2625
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