Subject: [sv-bc] RE: [sv-ec] 'Master' and 'slave' labels unacceptable
From: Jay Lawrence (lawrence@cadence.com)
Date: Wed Nov 26 2003 - 16:49:27 PST
I think it's time to rewrite all the interface examples Dave!
Thanks for the laugh, have a nice holiday.
jay
===================================
Jay Lawrence
Senior Architect
Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================
> -----Original Message-----
> From: Dave Rich [mailto:David.Rich@synopsys.com]
> Sent: Wednesday, November 26, 2003 6:10 PM
> To: sv-bc@eda.org; sv-ec@eda.org
> Subject: [sv-ec] 'Master' and 'slave' labels unacceptable
>
>
> If this becomes an errata, I'm quitting :-)
>
> http://www.cnn.com/2003/TECH/ptech/11/26/master.term.reut/index.html
>
> Happy Thanksgiving
>
> Dave
>
> --
> --
> David.Rich@Synopsys.com
> Technical Marketing Consultant
> http://www.SystemVerilog.org
> tele: 650-584-4026
> cell: 510-589-2625
>
>
>
This archive was generated by hypermail 2b28 : Wed Nov 26 2003 - 16:51:06 PST