Subject: [sv-bc] SV-BC issues from thomas Kruse
From: Dave Rich (David.Rich@synopsys.com)
Date: Mon Dec 08 2003 - 08:57:52 PST
I propose that the following issues sent by Thomas be closed
80 - The definition is not legal because it mixes procedural and labeled
fields
83 - Now a duplicate of 54
84 - Duplicate of 54
85 - This is defined in IEEE 1364 spec
86 - For integral types, the rules are the same as Verilog. Other types
have valid operators listed in the data type section
88 - Duplicate of 70 - Proposal for 70 now includes the stronger wording
89 - Different wording for the same functionality
90 - In 3.1 logic and reg have been made indistinguishable
This leaves only 92 still open, which should be discussed in committee
(I thought another proposal already covered this, but can't find it)
-- -- David.Rich@Synopsys.com Technical Marketing Consultant http://www.SystemVerilog.org tele: 650-584-4026 cell: 510-589-2625
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