Subject: Re: [sv-bc] SV-BC issues from thomas Kruse
From: Dave Rich (David.Rich@synopsys.com)
Date: Thu Dec 11 2003 - 09:02:52 PST
'signal' is used throughout the IEEE 1364-2001 spec, and is used with
the same meaning in SV and VHDL. (Any identifier whose value change
creates an event, i.e. signals an event)
Shalom.Bresticker@motorola.com wrote:
>In 85, Thomas wrote:
>
> What is the definition of 'signal'?
> What is the definition of 'scalar'?
>
>'scalar' is indeed defined in IEEE 1364-2001 in section 3.3:
>"A net or reg declaration without a range specification shall be considered 1 bit wide and is known as a scalar."
>
>However, 'signal' is not defined.
>
>Shalom
>
>
>On Mon, 8 Dec 2003, Dave Rich wrote:
>
>
>
>>I propose that the following issues sent by Thomas be closed
>>
>>85 - This is defined in IEEE 1364 spec
>>
>>
>
>
>
-- -- David.Rich@Synopsys.com Technical Marketing Consultant http://www.SystemVerilog.org tele: 650-584-4026 cell: 510-589-2625
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