Subject: [sv-bc] errata - missing section heading for extern modules
From: Dave Rich (David.Rich@synopsys.com)
Date: Mon Jan 05 2004 - 08:41:25 PST
A new section called "Extern Modules" should precede the following
paragraph in section 18.6
_18.7 Extern Modules
_
To support separate compilation, extern declarations of a module can be
used to declare the ports on a module
without defining the module itself....
-- -- David.Rich@Synopsys.com Technical Marketing Consultant http://www.SystemVerilog.org tele: 650-584-4026 cell: 510-589-2625
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