Subject: [sv-bc] Dave Rich & Peter Flakes comments on Cliff's interface proposal
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Thu Jan 08 2004 - 12:53:24 PST
Hi, All -
Johny asked me to review comments from Dave Rich and Peter Flake on the
interface section proposal. I believe both comments offer improvements to
the proposal, except I think Peter's comment should be friendly-amended to
move the suggested paragraph even earlier in the section.
I have attached the proposal with these two friendly amendments.
Dave Rich's new wording is shown in the first paragraph of section 19.4.2
Peter's suggested re-ordering, along with my added re-ordering (no text
changes) is shown in section 19.4.
If there are no objections, I propose that we send the friendly-amended
version to David Smith for submission to the next possible SV 3.1a draft.
Regards - Cliff
At 05:25 AM 1/8/2004, Srouji, Johny wrote:
>Hi All,
>
>...
>Decision: Proposal PASSES.
>
>Cliff, can you please review the following comments sent by Dave and Peter?
I agree with Dave Rich's friendly amendment. His description is an
improvement. Unless there is objection, I believe this should be considered
a friendly amendment and included.
>Following are comments sent by Dave Rich:
> >>>>>>>>>>>>>>>>>>>>>>
>I did find one grammar correction needed in section 19,4,2
>
>This interface example shows how to use modports to control signal
>directions _restrict signal interface access and direction_ . It uses
>the modport name in the module instantiation.
>
>
>Should be
>
>This interface example shows how to use modports to control signal
>directions _restrict interface __ signal __access and control their
>direction_ . It uses the modport name in the module instantiation.
> >>>>>>>>>>>>>>>>>>>>>>
Peter has just suggested an ordering change with no textual changes. After
reading Peter's comments, I agree that the paragraph should be moved
earlier (before the example) but after looking closer, I think the
paragraph should be moved up one more paragraph so that it directly follows
the example in question. Then the paragraph:
The modport list name (master or slave) can also be specified in the port
connection with the module instance, where the modport name is hierarchical
from the interface instance.
is followed immediately by the corresponding example.
What do people think? No text changes, just text movement closer to the
corresponding examples. See section 19.4 on Modports.
>Following are comments sent by Peter Flake:
> >>>>>>>>>>>>>>>>>>>>>>
>
>I vote in favour of Cliff's proposal, but I have noticed that it would be
>clearer if the following text and example were swapped, since the text
>refers to the previous example.
>
>REPLACE
> module m (i2 i);
> ...
>endmodule
>
>module s (i2 i);
> ...
>endmodule
>
>module top;
> i2 i();
>
> m u1 (.i(i.master));
> s u2 (.i(i.slave));
>endmodule
>
>The syntax of interface_name.modport_name reference_name gives a local
>name for a hierarchical reference. Note that this can be generalized to
>any interface with a given modport name by writing interface.modport_name
>reference_name.
>
>WITH
>
>The syntax of interface_name.modport_name reference_name gives a local
>name for a hierarchical reference. Note that this can be generalized to
>any interface with a given modport name by writing interface.modport_name
>reference_name.
>
> module m (i2 i);
> ...
>endmodule
>
>module s (i2 i);
> ...
>endmodule
>
>module top;
> i2 i();
>
> m u1 (.i(i.master));
> s u2 (.i(i.slave));
>endmodule
>
> >>>>>>>>>>>>>>>>>>>>>>
>
> --- Johny.
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training
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