Subject: [sv-bc] SystemVerilog 3.1a Draft 3 - Stu-note on enumerated names/labels
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Fri Jan 23 2004 - 18:02:25 PST
Hi, All -
In section 3.10.2 on page 18 of the SV 3.1a Draft 3 LRM, Stu points out
that enum names/labels should be documented consistently throughout the
LRM. I agree.
Stu prefers "label."
I prefer "name" for two reasons:
(1) We have already added labels to SV (section 8.8)
(2) ModelSim and VCS have already implemented a ".name" modifier to
$display enumerated names. Example
enum {a, b, c} xxx;
$display ("%s", xxx.name); // .name required to see the string name
This works for both VCS and ModelSim to display the enumerated names. I
think someone said this came from a PLI enhancement which was defined for
handling enumerated names???
Whatever we decide, I don't think we have documented how to $display
enumerated names. We should choose something like:
$display ("%s", xxx); // name is shown automatically.
$display ("%s", xxx.name); // .name required but then what should be shown
for just xxx? Right now it comes up blank for both simulators.
$display ("%s", xxx.label); // .label required but same question as above.
Thoughts?
Regards - Cliff
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training
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