Re: [sv-bc] Possible erratum about localparam

Subject: Re: [sv-bc] Possible erratum about localparam
From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Sun Feb 08 2004 - 04:32:21 PST

• Next message: Mark Hartoog: "[sv-bc] LRM review ch 18."
• Previous message: Shalom Bresticker: "Re: [sv-bc] Hex escape codes in string literals"
• In reply to: Brad Pierce: "[sv-bc] Possible erratum about localparam"
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

Note that 1364 proposal on generates allows localparam declarations in generates
blocks.

Shalom

Brad Pierce wrote:

> In 5.3, the following --
>
> "SystemVerilog enhancements to parameter constant declarations
> are presented in Section 21. SystemVerilog does not change
> localparam and specparam constants declarations."
>
> should probably be changed to
>
> "SystemVerilog enhancements to parameter and localparam constant
> declarations are presented in Section 21. SystemVerilog does not
> change specparam constant declarations."
>
> because according to LRM 161 of Section 21, "SystemVerilog adds the
> ability for local parameters to be declared in a generate block."
>
> -- Brad

--
Shalom Bresticker                           Shalom.Bresticker@motorola.com
Design & Reuse Methodology                             Tel: +972 9 9522268
Motorola Semiconductor Israel, Ltd.                    Fax: +972 9 9522890
POB 2208, Herzlia 46120, ISRAEL                       Cell: +972 50 441478

• Next message: Mark Hartoog: "[sv-bc] LRM review ch 18."
• Previous message: Shalom Bresticker: "Re: [sv-bc] Hex escape codes in string literals"
• In reply to: Brad Pierce: "[sv-bc] Possible erratum about localparam"
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

This archive was generated by hypermail 2b28 : Sun Feb 08 2004 - 04:39:08 PST