[sv-bc] SV Full Committee Meeting on March 4, 2004

Subject: [sv-bc] SV Full Committee Meeting on March 4, 2004
From: Vassilios.Gerousis@infineon.com
Date: Mon Feb 09 2004 - 07:28:24 PST

• Next message: Brad Pierce: "[sv-bc] Typos in Section 19"
• Previous message: Mark Hartoog: "[sv-bc] LRM review ch 18."
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

Hi SV members,
        We do plan to have 1/2 a day of SV committee meeting. Our plan is to
discuss the following:

1- LRM Status.
2- Completion Of the 3.1A Standardization Process.
3- Review period during March time frame (Errata List).
4- Continuation of Review (Errata) beyond April release. Our Intention to is
collect many Errata during the months of April and May, Before We transfer
Accellera Standard to IEEE in June. Publication of Errata List with 3.1A.
5- Accellera Certification for SystemVerilog Compliance.
6- Activities/Inactivities prior to DAC 2004.
7- Future Activities By Accellera: (e.g. Acceleratable Verification Layer =
Testbench+Assertions).

Meeting Time 9:30 to 12:00 on March 4.
Place : Somewhere in San Jose Area.

Best Regards

Vassilios

• Next message: Brad Pierce: "[sv-bc] Typos in Section 19"
• Previous message: Mark Hartoog: "[sv-bc] LRM review ch 18."
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

This archive was generated by hypermail 2b28 : Mon Feb 09 2004 - 07:47:32 PST