[sv-bc] undefined terminology in section 7.19
Subject: [sv-bc] undefined terminology in section 7.19
From: Dave Rich (David.Rich@synopsys.com)
Date: Tue Feb 10 2004 - 22:13:17 PST
Section 7.19 has undefined terminology that can be replaced with
terminology that has been defined
REPLACE the marked text in section 7.19 conditional operator
SystemVerilog extends the conditional operator to non bit-level
integral types and aggregate
expressions using the following rules:
— If both first expression and second expression are bit-level
types, or a packed aggregate of bit integral type, the operation proceeds
as defined.
— If first expression or second expression is a bit-level an integral type and the opposing
expression can be implicitly cast to a bit-level
an integral type, the
cast is made and proceeds as defined.
--
--
David.Rich@Synopsys.com
Technical Marketing Consultant and/or
Principal Product Engineer
http://www.SystemVerilog.org
tele: 650-584-4026
cell: 510-589-2625
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