Subject: [sv-bc] Re: SV31A LRM interpretation for: unique case
From: Dave Lindner (dlindner@cadence.com)
Date: Tue Feb 17 2004 - 13:52:41 PST
SystemVerilog LRM says:
"A unique case shall guarantee no overlapping case values, allowing the case items to be evaluated in parallel."
Did you really mean matching multiple case values is an error,
or multiple matching case items is an error, which makes more sense?
What happens when:
There is one case item that has multiple true case expressions, and
all other case items have false case expressions.
We believe that this scenario, demonstrated in Example 1 should not throw a "unique" run-time error in the simulator.
Is our interpretation correct?
Example 1: Using "unique casex"
Assume "reg [3:0] value;" is equal to "4'b1111" when the following "unique casex" is executed:
unique casex (value)
'b111x, 'b11x1: $display( "case item 1 executed" ); //1st case item - has multiple true case expressions
'b1101: $display( "case item 2 executed" ); //2nd case item - has no true case expression
endcase
With value set to "4'b1111":
The first case item has multiple true case expressions.
All other case items have false case expressions.
We believe that this is not an error, based upon the following consistency argument, demonstrated in Example 2, which uses the "unique if" construct:
Example 2: Using "unique if"
Assume "reg [3:0] value, a, b;" are all equal to "4'b1111",
and "reg [3:0] c;" is equal to "4'b1101", when the when the following "unique if" is executed:
unique if ((value == a) || (value==b)) //1st "unique if" condition - is true in multiple ways
$display( "if clause 1 executed" );
else if (value == c) //2nd "unique if" condition - is false
$display( "if clause 2 executed" );
With value, a, b, c set to the above values:
The first "unique if" condition is true in multiple ways.
No other "unique if" condition is true.
We know that this should not throw a "unique" run-time error in the simulator.
Therefore the "unique casex" analogy should not throw a run time error.
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