Subject: Re: [sv-bc] Re: SV31A LRM interpretation for: unique case
From: Dave Rich (David.Rich@synopsys.com)
Date: Wed Feb 18 2004 - 11:51:13 PST
Stu,
The V2K LRM (BTW, I'm using version C now!) refers to ’b111x, ‘b11x1 as
case item expressions, and the collective expressions together with the
branch statement as a case item. So I think the wording is correct.
Also BTW, if you use unique casex and the case expression is X, that
will produce a violation. Don't use casex.
Dave
Stuart Sutherland wrote:
> Dave,
> One of the example previously given had multiple case items that could
> satisfy the same branch.
> ----------
>
> Example 1: Using “unique casex”
>
> Assume “reg [3:0] value;” is equal to “4’b1111” when the following
> “unique casex” is executed:
>
> unique casex (value)
>
> ’b111x, ‘b11x1: $display( “case item 1 executed” ); //1^st case item –
> has multiple true case expressions
>
> ’b1101: $display( “case item 2 executed” ); //2^nd case item – has no
> true case expression
>
> endcase
>
> ----------
> The given value of the case expression would only satisfy one branch
> of the code. If I understand correctly, your change means that this
> will still generate an error, because two case items are true for the
> same branch of code. Is that your intent?
> Note that in that example, if value were 'b1101, then two branches
> could be true, which would--and should--be an error.
> Stu
> ~~~~~~~~~~~~~~~~~~~~~~~~~
> Stuart Sutherland
> stuart@sutherland-hdl.com
> 503-692-0898
>
> ------------------------------------------------------------------------
> *From:* owner-sv-bc@server.eda.org
> [mailto:owner-sv-bc@server.eda.org] *On Behalf Of *Dave Rich
> *Sent:* Wednesday, February 18, 2004 12:20 AM
> *To:* Dave Lindner
> *Cc:* sv-bc@server.eda.org; Steven Sharp; Rick Sullivan
> *Subject:* Re: [sv-bc] Re: SV31A LRM interpretation for: unique case
>
> Dave,
>
> Yes I agree with your interpretation.
>
> I suggest the following errata for Section 8.4
>
> "A unique case shall guarantee no overlapping case values_items_,
> allowing the case items to be evaluated in parallel."
>
> Dave
>
>
> Dave Lindner wrote:
>
>> SystemVerilog LRM says:
>>
>> “A unique case shall guarantee no overlapping case values,
>> allowing the case items to be evaluated in parallel.”
>>
>> Did you really mean matching multiple case values is an error,
>>
>> or multiple matching case items is an error, which makes more sense?
>>
>> What happens when:
>>
>> There is one case item that has multiple true case expressions, and
>>
>> all other case items have false case expressions.
>>
>> We believe that this scenario, demonstrated in Example 1 should
>> *not* throw a “unique” run-time error in the simulator.
>>
>> Is our interpretation correct?
>>
>> Example 1: Using “unique casex”
>>
>> Assume “reg [3:0] value;” is equal to “4’b1111” when the
>> following “unique casex” is executed:
>>
>> unique casex (value)
>>
>> ’b111x, ‘b11x1: $display( “case item 1 executed” ); //1^st case
>> item – has multiple true case expressions
>>
>> ’b1101: $display( “case item 2 executed” ); //2^nd case item –
>> has no true case expression
>>
>> endcase
>>
>> With value set to “4’b1111”:
>>
>> The first case item has multiple true case expressions.
>>
>> All other case items have false case expressions.
>>
>> We believe that this is *not* an error, based upon the following
>> consistency argument, demonstrated in Example 2, which uses the
>> “unique if” construct:
>>
>> Example 2: Using “unique if”
>>
>> Assume “reg [3:0] value, a, b;” are all equal to “4’b1111”,
>>
>> and “reg [3:0] c;” is equal to “4’b1101”, when the when the
>> following “unique if” is executed:
>>
>> unique if ((value == a) || (value==b)) //1^st “unique if”
>> condition – is true in multiple ways
>>
>> $display( “if clause 1 executed” );
>>
>> else if (value == c) //2^nd “unique if” condition – is false
>>
>> $display( “if clause 2 executed” );
>>
>> With value, a, b, c set to the above values:
>>
>> The first “unique if” condition is true in multiple ways.
>>
>> No other “unique if” condition is true.
>>
>> We know that this should *not* throw a “unique” run-time error in
>> the simulator.
>>
>> Therefore the “unique casex” analogy should *not* throw a run
>> time error.
>>
>
>--
>--
>David.Rich@Synopsys.com
>Technical Marketing Consultant and/or
>Principal Product Engineer
>http://www.SystemVerilog.org
>tele: 650-584-4026
>cell: 510-589-2625
>
>
>
-- -- David.Rich@Synopsys.com Technical Marketing Consultant and/or Principal Product Engineer http://www.SystemVerilog.org tele: 650-584-4026 cell: 510-589-2625
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