Subject: [sv-bc] Re: [sv-cc] RE: [sv-ec] Agenda And Plans For Full SV Meeting IN Mountain Views
From: Karen Pieper (Karen.Pieper@synopsys.com)
Date: Tue Mar 02 2004 - 17:50:24 PST
This bounced from the user.
K
>From: Michael Rohleder <michael.rohleder@motorola.com>
>Reply-To: Michael.Rohleder@motorola.com
>Organization: Motorola Semiconductor Products Sector
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>To: "David W. Smith" <dwsmith@synopsys.com>, Vassilios.Gerousis@infineon.com
>CC: sv-ac@server.eda.org, sv-bc@server.eda.org, sv-cc@server.eda.org,
> sv-ec@server.eda.org
>Subject: Re: [sv-cc] RE: [sv-ec] Agenda And Plans For Full SV Meeting IN Mountain
> Views
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>
>Hi all,
>
>I am a little amazed that the bullet #5 of the original agenda:
> 5- Accellera Certification for SystemVerilog Compliance.
>has been gone. This would have been a Good Thing (tm).
>
>I am often bogged down by the support and non-support of Verilog-2001 constructs by tools (we are in the year 2004, only 3 years
>after _releasing_ the standard).
>
>The problem is simple: if there is only one tool within the whole tool chain that does not support a certain construct, then you are
>back at square 1 (Verilog-1995). You have the choice to either omit this tool (which is sometimes not possible) or not to use this
>construct. At the end you might end up with just using the least common denominator (which might be VL-1995 again).
>
>If the future support of SystemVerilog continues to be in a similar fashion ... hmmm.
>
>I would have loved to see a definition of the minimum subset that must be fully supported when a tool wants to claim it supports
>SystemVerilog. Or a layered approach, like the NEXUS standard (IEEE Std 1500) defined.
>
>Anything here would be better than just ignoring this problem. Just my 0.02 EUR to the adoption process.
>
>Best regards,
>-Michael
>
>
>"David W. Smith" wrote:
>
>> I have heard that some people have not seen this. Here is a resend.
>>
>> Regards
>> David
>>
>> -----Original Message-----
>> From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Vassilios.Gerousis@infineon.com
>> Sent: Wednesday, February 25, 2004 9:22 PM
>> To: sv-ac@eda.org; sv-bc@eda.org; sv-cc@eda.org; sv-ec@eda.org
>> Subject: [sv-ec] Agenda And Plans For Full SV Meeting IN Mountain Views
>>
>> Hi SV members,
>>
>> Synopsys volunteered to host Accellera SV full committee meeting.
>> Synopsys, Inc.
>> <http://www.synopsys.com/cgi-bin/mapquest/mqinterconnect?streetaddress=700+E> ast+Middlefield+Rd&city=Mountain+View&state=CA&zip=94043>
>> 700 East Middlefield Road
>> Mountain View, CA 94043
>> Building B
>> The Diamond Conference
>>
>> It is planned for March 4, Thursday. The meeting will start at 9:30 and
>> finish at 12:00. The primary goal is to discuss the current status of the
>> LRM, voting process, and the continuation of Errata list.
>>
>> 1- Committee status.
>> 2- JEITA Activities with SystemVerilog.
>> 3- LRM status, including BNF.
>> 4- Issues.
>> 5- Accellera efforts to move forward with other activities related to
>> SystemVerilog:
>> a- SystemVerilog Acceleration Working Group.
>> b- Modeling Group.
>> c- SystemVerilog-AMS (engagement with Verilog-AMS committee).
>> d- Others.
>>
>> Please send me your name so that we can pre-register you for
>> attending the attending. We will provide a teleconference number. Seating is
>> limited to 15. 6 of the available space are reserved for SystemVerilog
>> chairs. You must pre-register to attend.
>>
>> Vassilios
>
>--
>
>NOTE: The content of this message may contain personal views
> which are not neccessarily the views of Motorola, unless specifically stated.
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