There is an additional change to 5.6 at the end which addresses the missing section cross reference. Please include it.

Section 15.12

LRM-195

Changes (Was not done):

Swap Section 15.12 and 15.13

Section 15.15/15.15.1

What happened. 15.4 was Synchronous drives with sub-sections 15.14.1 and 15.14.2. In your new draft it became 15.4, 15.5, and 15.15.1? I think it was correct the other way.

Section 16

OK

Section 17

OK

Section 18.7.3

LRM-25

Changes (on each change you left off the . Any reason?):

A .name .port_identifier port connection is semantically equivalent to the named port connection .port_identifier(name) .name(name) port connection with the following exceptions:

The identifier referenced by .name .port_identifier shall not create an implicit wire declaration.

— It shall be illegal for a .name .port_identifier port connection to create an implicit cast. This includes truncation or padding.

— A conversion between a 2-state and 4-state type of the same bit length is a legitimate cast.

— A port connection between a net type and a variable type of the same bit length is a legitimate cast.

— It shall be an error if a .name .port_identifier port connection between two dissimilar net types would generate a warning message as required by the Verilog-2001 standard.

Section 19

OK

Section 26

OK

Section 27.3.2

Did you intend to leave the 1-5 non-indented?

Section 28

OK

Section A.1.5

LRM-252

Changes (I messed up, the first line after bind needs to be deleted and not changed- the following is the correct production):

bind_directive ::=

bind module_instance_identifier program_instance_identifier ;

bind module_identifier bind_instantiation ;

| bind name_of_instance bind_instantiation ;

Section A.2.10

LRM-252

Changes (I got the second line in the production wrong, please correct):

boolean_abbrev ::=

repeat_operator consecutive_repetition

| nth_event_operator non_consecutive_repetition

| counting_operator goto_repetition

Section A.6.3

LRM-176 LRM_252

Changes (you changed the else clause. How come?):

action_block ::=

[ statement ] [ else statement ] ; statement _or_null

| [ statement ] else statement_or_null

Section A.6.10

The indent on the first clause of the concurrent_cover_statement is not indented correctly.

You are correct (my fault). Please remove the editor’s note.

Editor’s Note: Both productions above were identical in the change order. I am guessing that the first one was supposed to be “property_spec“.

Section A.9.3

LRM-59

Changes (you missed one):

real_identifier ::= identifier

LRM-60

Changes (and another):

state_identifier ::= identifier

LRM-252

Changes (and another):

template_identifier ::= identifier

Section B

OK

Section C.5.15

True, but it can never be used where a member is used so I do not believe there is a conflict.

Editor’s Note: “assign” is a Verilog keyword.

Section D

OK

Section G

OK

Index

LRM 128

Change (Need to add to index):

specparam 241

srandom ???

statement labels 64

Change (Need to add to index):

unsized literals 4

urandom ???

urandom_range ???

user-defined types 17

Section 5.6

Change:

SystemVerilog variables may be packed or unpacked aggregates of other types. The assignments made to each element of a variable are independently examined using the longest static prefix rules (see section TDB- SVBC21). [Note: This will define an assignment like a[i] = expr; to be treated as an assignment to all elements of an array] Multiple assignments made to independent elements of a variable are examined individually. An assignment where the left-hand-side contains a slice is treated as a single assignment to the entire slice. It shall be an error to have a packed structure or array type written with a mixture of procedural and continuous assignments. Thus, an unpacked structure or array can have one element assigned procedurally, and another element assigned continuously. And, each element of a packed structure or array may each have a single continuous assignment. For example, assume the following structure declaration: