Proposal: Reconciliation of SystemVerilog BNF with 5 recent Verilog errata fixes
: 5/Sept/2003
---- ETF 182 ----------------------------------------------------------------------------------------
In A.6.5, change
event_identifier
to
hierarchical_event_identifier
---- ETF 194----------------------------------------------------------------------------------------
In A.9.1, change –
attr_spec ::= attr_name = constant_expression
| attr_name
to
attr_spec ::= attr_name [ = constant_expression ]
---- ETF 231 ----------------------------------------------------------------------------------------
Move function_statement_or_null from A.6.2 to A.6.4.
---- ETF 259 ----------------------------------------------------------------------------------------
In A.9.3, change
text_macro_identifier ::= simple_identifier
to
text_macro_identifier ::= identifier
---- ETF 338 ----------------------------------------------------------------------------------------
In A.7.4, the RHS of parallel_edge_sensitive_path_description and of full_edge_sensitive_path_description should require parentheses.
Specifically, change
parallel_edge_sensitive_path_description ::=
( [ edge_identifier ] specify_input_terminal_descriptor =>
specify_output_terminal_descriptor [ polarity_operator ] : data_source_expression )
full_edge_sensitive_path_description ::=
( [ edge_identifier ] list_of_path_inputs *>
list_of_path_outputs [ polarity_operator ] : data_source_expression )
to
parallel_edge_sensitive_path_description ::=
( [ edge_identifier ] specify_input_terminal_descriptor =>
( specify_output_terminal_descriptor [ polarity_operator ] : data_source_expression ) )
full_edge_sensitive_path_description ::=
( [ edge_identifier ] list_of_path_inputs *>
( list_of_path_outputs [ polarity_operator ] : data_source_expression ) )