Section 11.23, 19.7, 20.2, A.1.4, Syntax 20-1
Parameter port lists

In section A.1.4, REPLACE

parameter_port_list ::= # ( parameter_declaration { , parameter_declaration } )

WITH

parameter_port_list ::=

# ( list_of_param_assignments { , parameter_port_declaration } )

| # ( parameter_port_declaration { , parameter_port_declaration } )

parameter_port_declaration ::=

parameter_declaration

| data_type list_of_param_assignments

| type list_of_type_assignments

and ADD the productions for parameter_port_list and parameter_port_declaration to Syntax 20-1 along with a comment that

// from Annex A.1.4

In 20.2, REPLACE

A module or interface can have parameters

WITH

A module, interface, program or class can have parameters

In 20.2, APPEND the following text to the end of the section

SystemVerilog also adds the ability to omit the parameter keyword in a parameter port list.

class vector #(size = 1);

logic [size-1:0] v;

endclass

typedef vector#(16) word;

interface simple_bus #(AWIDTH = 64, type T = word)

(input bit clk) ;

endinterface

In 11.23, in the examples, REPLACE both occurrences of

#(parameter int size = 1;)

WITH

#(int size = 1)

and REPLACE

#(parameter type T = int;)

WITH

#(type T = int)

In 19.7, REPLACE

#(parameter AWIDTH = 8, DWIDTH = 8)

WITH

#(AWIDTH = 8, DWIDTH = 8)