Proposal for SV-BC Issue 75

This proposal is just a clarification on “Parameter dependence”, which is already allowed and explained in the Verilog 2001 LRM Section 12.2.3. This clarification illustrates how it extends to type parameters, which are new to SystemVerilog.

Add the following text at the end of Section 20. Note that it follows the proposal to drop the parameter keyword in #( ) lists.

In a list of parameters, a parameter can depend on earlier parameters. In the following declaration, the default value of the second parameter depends on the value of the first parameter. The third parameter is a type, and the fourth parameter is a value of that type.

module mc # (int N = 5, M = N*16, type T = int, T x = 0)

( ... );

...

endmodule