Main Process Bullets and timelines:

- Draft-5 of SV3.1 LRM was made available on Friday February 27^th. It was parked under: http://www.eda.org/sv/SystemVerilog_3.1a_draft5.pdf

- By March 10^th: Committee members to review draft-5 and send comments or corrections into sv-bc. Only editorial comments are considered.

- on March 10^th - Johny and Karen will prepare a list and send to David Smith (owner of the LRM)

- If the amount of issues that were found during the review period (ending by March 10^th) is sufficient, a Draft-6 shall be created including these changes.

- Any requested changes made after March 10^th shall not be accepted

- Voting on Draft-5 and proposed changes will occur in our meeting at March 15^th. This allows 5 days period for the review and voting to occur.

- Only qualified voting members are eligible to vote.

- On March 31^st - TCC will provide recommendation to Accellera board

- On April 15^th - Accellera board ill complete the voting and approve SV3.1A as an Accellera standard

- On April 8 - all editorial changes will be added to the final LRM of 3.1A. This version will be released on April 15.

- Between April 8 through June 1^st, SV committees will continue to collect feedback (Errata and Enhancement):

o Errata will be released on biweekly basis on the reflector.

o Errata list will be released separately from the original Standard. We will have versions attached to it.