Section 2.7, 2.8, 3.3.1, 3.14, 5.8, 7.13, 7.14, 7.16, 18.9, 19.4.4, 23.2, A.2.2.1, A.8.4, Syntax 3-6
Aggregate constructors

In 2.7, REPLACE

If the type is not given by the context, it must be specified with a cast.

WITH

If the type is not given by the context, it must be specified with a cast. Array literals are constant unpacked array constructors (see Section 7.13). An array literal must have a type, which may be either explicitly indicated with a prefix or implicitly indicated by an assignment-like context (see Section 3.14).

In 2.7, REPLACE

b = {1:1, default:0};

WITH

triple b = {1:1, default:0};

In 2.8, REPLACE

Structure literals must have a type, either from context or a cast.

WITH

Structure literals are constant structure constructors (see Section 7.14). Structure literals A structure literal must have a type, either from context or a cast which may be either explicitly indicated with a prefix or implicitly indicated by an assignment-like context (see Section 3.14).

In 3.3.1, APPEND the following paragraph to the end of the section

The term simple bit vector type is used throughout this document to refer to the data types that can directly represent a one-dimensional packed array of bits. The packed vector types of Verilog-2001 are simple bit vector types, as are the integral types with predefined widths, such as byte. The SystemVerilog packed structure types and multidimensional packed array types are not simple bit vector types, but each is equivalent (see Section 5.8.2) to some simple bit vector type, to and from which it can be easily converted.

In 3.14, REPLACE the title

Casting

WITH

Casting and aggregate construction

In Syntax 3-6, REPLACE the caption

casting

WITH

casting and aggregate construction

In A.8.4, in constant_primary, REPLACE

| constant_cast

WITH

| constant_cast_or_constructor

In A.8.4, in primary, REPLACE

| cast

WITH

| cast_or_constructor

In A.8.4 and Syntax 3-6, REPLACE

constant_cast ::=

casting_type ' ( constant_expression )

| casting_type ' constant_concatenation

| casting_type ' constant_multiple_concatentation

cast ::=

casting_type ' ( expression )

| casting_type ' concatenation

| casting_type ' multiple_concatentation

WITH

constant_cast_or_constructor ::=

casting_type ' ( constant_expression )

| [ casting_type ] ' constant_concatenation

| [ casting_type ] ' constant_multiple_concatentation

cast_or_constructor ::=

casting_type ' ( expression )

| [ casting_type ] ' concatenation

| [ casting_type ] ' multiple_concatentation

In A.2.2.1 and Syntax 3-6, REPLACE

casting_type ::= simple_type | size | signing

WITH

casting_type ::= simple_type | constant_primarysize | signing

In A.2.2.1 and Syntax 3-6, in simple_type, ADD

| ps_parameter_identifier

In 3.14 (as amended by erratum 111), REPLACE

The expression to be cast must be enclosed in parentheses or within concatenation or replication braces and the expression shall be determined in the context of an assignment to the target type. When using braces, the context of the braces shall also be determined by the target type.

int'(2.0 *3.0)

shortint'{8'hFA,8'hCE}

WITH

In a static cast the The expression to be cast must shall be enclosed in parentheses or within concatenation or replication braces and the expression shall be determined in the context of an assignment to the target type that are prefixed with the casting type and an apostrophe, unless the expression to be cast is a concatenation or replication and the casting type is a simple bit vector type or a signing or size (see below), in which case the parentheses can be omitted. If the expression is assignment compatible with the casting type, then the cast shall return the value that a variable of the casting type would hold after being assigned the expression. If the expression is not assignment compatible with the casting type, then if the casting type is an enumerated type, the behavior shall be as described as in Section 3.15, and if the casting type is a bit-stream type, the behavior shall be as described in Section 3.16.

int'(2.0 *3.0)

shortint'{8'hFA,8'hCE}

When using braces the context of the braces shall also be determined by the target type. SystemVerilog extends the concatenation and replication syntax of Verilog-2001 to support the construction of unpacked arrays, as well as of SystemVerilog structures and multidimensional packed arrays (see Sections 7.13 and 7.14). In these aggregate constructors each member expression shall be assignment compatible with the type of the corresponding structure field or array element and shall be evaluated as if it were the right-hand value of an assignment to a variable of that type.

typedef struct packed {shortint x, y;} my_int;

int i = my_int'{8'hFA,8'hCE}; // i is assigned 32'h00FA00CE

When an aggregate constructor is used as the right-hand value in an assignment-like context (see below):

- If the left-hand value is of an aggregate type, the explicit type prefix can be omitted.

- If the left-hand value is of a packed structure type or of a multidimensional packed array type:

n If a label, index, type, or default key is used, then the explicit type prefix can be omitted.

n If no key is used, then an apostrophe can be used instead of the explicit type prefix.

my_int j = '{8'hFA,8'hCE}; // {j.x,j.y} is assigned 32'h00FA00CE

my_int k = {8'hFA,8'hCE}; // {k.x,k.y} is assigned 32'h0000FACE

byte A[N] = {0:1, default:0};

logic [N-1:0][7:0] B = {N-1:1, default:0};

When it is legal to omit the explicit type prefix, it shall also be legal to use an apostrophe instead of the explicit type prefix.

byte C[5] = '{0,1,2,3,4}; // the ' is legal, but not required

An assignment-like context is:

n A continuous or procedural assignment

n For a parameter with an explicit type declaration:

--- A parameter value assignment in a module, interface, program or class

--- A parameter value override in the instantiation of a module, interface, or program that is declared in the compilation unit scope

--- A parameter value override in the instantiation of a class or in the left-hand side of a class scope operator

n A port connection to an input port of a module, interface, or program that is declared in the compilation unit scope

n The passing of a value to a subroutine input port

n A return statement in a function

n For an expression that is used as the right-hand value in an assignment-like context

--- If a parenthesized expression, then the expression within the parentheses

--- If a mintypmax expression, then the colon-separated expressions

--- If a conditional operator expression, then the second and third operand

n A non-default correspondence between an aggregate constructor member expression and a structure field or array element

A static cast or a default correspondence between an aggregate constructor or packed structure constructor member expression and a structure field or array element shall not be considered an assignment-like context.

In 3.14, DELETE

A user-defined type can be used.

mytype’(foo)

In 7.13, REPLACE the section title

Unpacked array expressions

WITH

Unpacked aArray constructors expressions

In 7.13 REPLACE

Braces are also used for expressions to assign to unpacked arrays.

WITH

Verilog-2001 uses concatenation braces to construct simple bit vectors. SystemVerilog extends that syntax to support the construction of unpacked arrays and multidimensional packed arrays. Braces are also used for expressions to assign to unpacked arrays.

In 7.13 REPLACE

The syntax of multiple concatenations can be used for unpacked array expressions as well.

WITH

The syntax of multiple concatenations can be used for unpacked array constructors expressions as well.

In 7.13, REPLACE

If used in the context of an assignment to an unpacked array, the braces represent an unpacked array literal or expression. Outside the context of an assignment on the right hand side, an explicit cast must be used with the braces to distinguish it from a concatenation.

WITH

If used in the context of as the right-hand value in an assignment to an unpacked array, the braces represent an unpacked array literal or constructor expression. Outside an assignment-like the context of an assignment on the right-hand side, an explicit cast type prefix must be used (see Section 3.14) with the braces to distinguish it from a concatenation.

In 7.13, REPLACE

Note an aggregate expression cannot be used as the target of an assignment.

WITH

Note an aggregate constructor expression cannot be used as the target of an assignment.

In 7.13, REPLACE

initial unpackedints = {default:2}; // sets elements to 2

WITH

initial unpackedints = {default:2}; // sets elements to 2

When the expression after the default keyword is itself an aggregate constructor, an explicit type prefix shall be used.

In 7.13, REPLACE

When the braces include a type, or default key, the braces shall not be interpreted as a concatenation for both packed and unpacked array types.

WITH

When the braces include an index, type, or default key, the braces shall not be interpreted as a concatenation, but as an array constructor, for both packed and unpacked array types. When an array constructor is assigned to a left-hand value that is of a simple bit vector type, an explicit type prefix shall be used.

In 7.14, REPLACE the section title

Structure expressions

WITH

Structure constructors expressions

In 7.14, REPLACE

A structure expression (packed or unpacked) can be built from member expressions using braces and commas

WITH

A structure constructor expression (packed or unpacked) can be built from member expressions using braces and commas

In 7.14, REPLACE

If used in the context of an assignment to an unpacked structure, the braces represent an unpacked structure literal or expression. Outside the context of an assignment to an aggregate type, an explicit cast must be used with the braces to distinguish it from a concatenation. When the braces include a label, type, or default key, the braces shall not be interpreted as a concatenation for both packed and unpacked structure types.

WITH

If used in the context of as the right-hand value in an assignment to an unpacked structure, the braces represent an unpacked structure literal or constructor expression. Outside an assignment-like the context of an assignment to an aggregate type, an explicit type prefix cast must be used (see Section 3.14) with the braces to distinguish it from a concatenation. When the braces include a label, type, or default key, the braces shall not be interpreted as a concatenation, but as a structure constructor, for both packed and unpacked structure types. When a structure constructor is assigned to a left-hand value that is of a simple bit vector type, an explicit type prefix shall be used.

In 7.14 (as amended by erratum 108), REPLACE

The expression after the default keyword shall not itself be a structure expression or structure literal unless an explicit cast is used.

WITH

The When the expression after the default keyword shall not is itself be an aggregate constructor, a structure expression or structure literal unless an explicit type prefix cast is shall be used.

In 7.14, REPLACE

The type:value specifies an explicit value for a field in the structure which is equivalent to the type and has not been set by a field name key above.

WITH

The type:value specifies an explicit value for a each field in the structure which whose type is equivalent matches to the type (see Section 5.8.1) and has not been set by a field name key above.

In 23.2 (regarding $typeof), REPLACE

When used in a comparison, equality ( == ) or case equality ( === ) is true if the operands are type equivalent (see Section 5.8, Type equivalency).

WITH

When used in a comparison, equality ( == ) or case equality ( === ) is true if the operands are type equivalent match (see Section 5.8.1, Type equivalency).

In 7.16, REPLACE

Unpacked structure and array variables, literals, and expressions can all be used as aggregate expressions.

WITH

Unpacked structure and array variables, literals, and unpacked structure and array constructors expressions can all be used as aggregate expressions.

In 18.9, REPLACE

SystemVerilog adds an explicitly named port declaration to that style, allowing elements of arrays and structures, concatenations of elements, or aggregate expressions of elements declared in a module, interface or program to be specified on the port list.

WITH

SystemVerilog adds an explicitly named port declaration to that style, allowing elements of arrays and structures, concatenations of elements, or aggregate constructors expressions of elements declared in a module, interface or program to be specified on the port list.

In 18.9, REPLACE

If the port expression is to be an aggregate expression, then a cast must be used since self-determined aggregate expressions are not allowed.

WITH

If the port expression is to be an aggregate constructor expression, then an explicit type prefix cast must shall be used since self-determined aggregate expressions are not allowed. Because an aggregate constructor cannot be used as the target of an assignment (see Section 7.13), it shall be illegal to declare a port using an aggregate constructor unless it is an output port.

In 19.4.4, REPLACE

A modport expression allows elements of arrays and structures, concatenations of elements, aggregate expressions of elements declared in an interface to be included in a modport list.

WITH

A modport expression allows elements of arrays and structures, concatenations of elements, aggregate constructors expressions of elements declared in an interface to be included in a modport list.

In 19.4.4, REPLACE

If the port expression is to be an aggregate expression, then a cast must be used since self-determined aggregate expressions are not allowed.

WITH

If the port expression is to be an aggregate constructor expression, then a cast an explicit type prefix must shall be used since self-determined aggregate expressions are not allowed. Because an aggregate constructor cannot be used as the target of an assignment (see Section 7.13), it shall be illegal to use an aggregate constructor as a port expression unless it is for an output port.

 In 5.8, REPLACE

Some SystemVerilog constructs and operations require a certain level of type compatibility for their operands to be legal. There are four levels of type compatibility, formally defined here: Equivalent, Assignment Compatible, Cast Compatible, and Non-Equivalent.

Note that there is no category for identical types defined here because there is no construct in the SystemVerilog language that requires it. For example, as defined below, int can be interchanged with bit signed [0:31] wherever it is syntactically legal to do so. Users can define their own level of type identity by using the $typename system function (see Section 23.3, Typename function), or through use of the PLI.

WITH

Some SystemVerilog constructs and operations require a certain level of type compatibility for their operands to be legal. There are four five levels of type compatibility, formally defined here: Matching, Equivalent, Assignment Compatible, Cast Compatible, and Non-Equivalent.

Note that there is no category for identical types defined here because there is no construct in the SystemVerilog language that requires it. For example, as defined below, int can be interchanged with bit signed [0:3131:0] wherever it is syntactically legal to do so. Users can define their own level of type identity by using the $typename system function (see Section 23.3, Typename function), or through use of the PLI.

In 5.8, RENUMBER

5.8.1 to 5.8.2

5.8.2 to 5.8.3

5.8.3 to 5.8.4

5.8.4 to 5.8.5

In 7.16, REPLACE

Section 5.8.2

WITH

Section 5.8.23

In each of 10.4.2, 18.12.1 and 19.6.1, REPLACE

Section 5.8.1

WITH

Section 5.8.12

In the renumbered 5.8.2 (formerly 5.8.1), REPLACE

An anonymous enum, struct, or union type is equivalent to itself among variables declared within the same declaration statement and no other types.

WITH

An anonymous enum, unpacked struct, or unpacked union type is equivalent to itself among variables declared within the same declaration statement and no other types.

In 5.8, ADD the following new Section 5.8.1

5.8.1 Matching Types

Two data types shall be defined as matching data types using the following inductive definition. If two data types do not match using the following definition, then they shall be defined to be non-matching.

1) Any built-in type matches every other occurrence of itself, in every scope.

2) A simple typedef or type parameter override that renames a built-in or user defined type matches that built-in or user defined type within the scope of the type identifier.

typedef bit node; // ’bit’ and ’node’ are matching types

typedef type1 type2; // ’type1’ and ’type2’ are matching types

3) An anonymous enum, struct, or union type matches itself among variables declared within the same declaration statement and no other types.

struct packed {int A; int B;} AB1, AB2; // AB1, AB2 have matching types

struct packed {int A; int B;} AB3; // the type of AB3 does not match the type of AB1

4) A typedef for an enum, struct, union, or class matches itself and the type of variables declared using that type within the scope of the type identifier.

typedef struct packed {int A; int B;} AB_t;

AB_t AB1; AB_t AB2; // AB1 and AB2 have matching types

typedef struct packed {int A; int B;} otherAB_t;

otherAB_t AB3; // the type of AB3 does match the type of AB1 or AB2

5) A simple bit vector type that does not have a predefined width and one that does have a predefined width match if both are 2-state or both are 4-state, both are signed or both are unsigned, both have the same width, and the right range bound of the simple bit vector type without a predefined width is zero.

typedef bit signed [7:0] BYTE; // matches the byte type

typedef bit signed [0:7] ETYB; // does not match the byte type

6) Two array types match if they have the same number of unpacked dimensions and their slowest-varying dimensions have matching types and the same left and right range bounds. Note that the type of the slowest-varying dimension of a multidimensional array type is itself an array type.

typedef byte MEM_BYTES [256];

typedef bit signed [7:0] MY_MEM_BYTES [256]; // MY_MEM_BYTES matches MEM_BYTES

typedef logic [1:0] [3:0] NIBBLES;

typedef logic [7:0] MY_BYTE; // MY_BYTE and NIBBLES are not matching types

7) Explicitly adding signed or unsigned modifiers to a type that does not change its default signing, does not create a non-matching type.

typedef byte signed MY_CHAR; // MY_CHAR matches the byte type

8) A typedef for an enum, struct, union, or class type declared in a package always matches itself, regardless of the scope into which the type is imported. The scope of a type identifier includes the hierarchical instance scope. This means that each instance with a user-defined type declared inside the instance creates a unique type. To have type matching among multiple instances of the same module, interface, or program, a type must be declared at higher level in the compilation unit scope than the declaration of the module, interface or program, or imported from a package.