Section 8.4
unique selection statements

In 8.4, REPLACE

A unique case shall check for overlapping case items, allowing the case items to be evaluated in parallel. A unique case shall issue a warning message if more than one case item matches the case expression.

WITH

A unique case shall asserts that there are no check for overlapping case items, allowing hence that it is safe for the case items to be evaluated in parallel. In a unique case it shall be legal to evaluate a case item expression at any time after the evaluation of the case expression and before the evaluation of the corresponding comparison. A unique case shall be illegal if, for any such interleaving of evaluations and comparisons, more than one case item matches the case expression. For an illegal A unique case a simulator shall be required to issue a warning message, unless it can demonstrate a legal interleaving of evaluations and comparisons such that no more than one case item matches the case expression. To implement this requirement a simulator can continue the evaluations and comparisons after the termination of the usual linear search and even after the execution of the statement associated with the first matching case item. However, the statements associated with any additional matching case items shall not be executed.

In 8.4, REPLACE

bit [2:0] a;

unique case(a) // values 3,5,6,7 cause a run-time warning

0,1: $display("0 or 1");

2: $display("2");

4: $display("4");

endcase

priority casez(a) // values 4,5,6,7 cause a run-time warning

3’b00?: $display("0 or 1");

3’b0??: $display("2 or 3");

endcase

WITH

bit [2:0] a;

unique case(a) // values 3,5,6,7 cause a run-time warning

0,1: $display("0 or 1");

2: $display("2");

4: $display("4");

endcase

priority casez(a) // values 4,5,6,7 cause a run-time warning

3’b00?: $display("0 or 1");

3’b0??: $display("2 or 3");

endcase

In 8.4, REPLACE

SystemVerilog adds the keywords unique and priority, which can be used before an if. If either keyword is used, it shall be a run-time error for no condition to match unless there is an explicit else. For example:

unique if ((a==0) || (a==1)) $display("0 or 1");

else if (a == 2) $display("2");

else if (a == 4) $display("4"); // values 3,5,6,7 cause an error

priority if (a[2:1]==0) $display("0 or 1");

else if (a[2] == 0) $display("2 or 3");

else $display("4 to 7"); //covers all other possible values, so no error

A unique if indicates that there should not be any overlap in a series of if...else...if conditions, i.e. they should be mutually exclusive, allowing the expressions to be evaluated in parallel. A software tool shall issue an error if it determines that more than one condition is, or can be, true. A software tool shall also issue an error if it determines that no condition is true, or it is possible that no condition is true, and the final if does not have a corresponding else.

A priority if indicates that a series of if...else...if conditions shall be evaluated in the order listed. In the preceding example, if the variable a had a value of 0, it would satisfy both the first and second conditions, requiring priority logic. A software tool shall also issue an error if it determines that no condition is true, or it is possible that no condition is true, and the final if does not have a corresponding else.

WITH

SystemVerilog adds the keywords unique and priority, which can be used before an if. If either keyword is used, it shall be a run-time error warning for no condition to match unless there is an explicit else. For example:

unique if ((a==0) || (a==1)) $display("0 or 1");

else if (a == 2) $display("2");

else if (a == 4) $display("4"); // values 3,5,6,7 cause an error warning

priority if (a[2:1]==0) $display("0 or 1");

else if (a[2] == 0) $display("2 or 3");

else $display("4 to 7"); //covers all other possible values, so no error warning

A unique if indicates asserts that there should not be any is no overlap in a series of if...else...if conditions, i.e., they should be are mutually exclusive, allowing hence that it is safe for the expressions to be evaluated in parallel. In a unique if it shall be legal for a condition to be evaluated at any time after entrance into the series and before the value of the condition is needed. A unique if shall be illegal if, for any such interleaving of evaluation and use of the conditions, more than one condition is true. For an illegal unique if A a software tool shall be required to issue an error warning, unless it can demonstrate a legal interleaving such if it determines that no more than one condition is, or can be, true. To implement this requirement a simulator can continue the evaluation of conditions after a first true condition has been found and even after the execution of the statement associated with the first true condition. However, the statements associated with any additional true conditions shall not be executed. A software tool shall also issue an error warning if it determines that no condition is true, or it is possible that no condition is true, and the final if does not have a corresponding else.

A priority if indicates that a series of if...else...if conditions shall be evaluated in the order listed. In the preceding example, if the variable a had a value of 0, it would satisfy both the first and second conditions, requiring priority logic. A software tool shall also issue an error warning if it determines that no condition is true, or it is possible that no condition is true, and the final if does not have a corresponding else.